many times, I develop my project in CoDeveloper, I works all ok in Codeveloper.
But when alfter generating HDLs, It can't work.
Is there any method to find out what the problem is ?
or any method to investigate the HDLs, Does HDLs really equals to the C code?
I am using an embedded CPU, many many times, I unluckilly encounted this problem, but helpless....

Hi Robin,

Several tools can help you diagnose the hardware design.

You can do an HDL simulation of the output from CoDeveloper to verify its correctness. HDL simulators, such as Mentor Graphics' ModelSim, can simulate the hardware logic created from Impulse C code. A new feature introduced with CoDeveloper 3.50, called the CoValidator HDL Testbench Generator, can help. This tool generates an HDL testbench, using test vector data created by running the usual desktop simulation, that you can easily run in ModelSim with a single command. The HDL testbench generates output test vectors as it runs, which you can then compare to those generated by desktop simulation.

CoValidator requires an additional feature in the Impulse license file, so please contact info@impulsec.com for an updated license.

Another method of verifying hardware behavior involves an "embedded logic analyzer". These tools, such as Altera's SignalTap and Xilinx' ChipScope, let you trace activity on signals within your design as it runs, logging data to a file on your PC.

Finally, even if simulation succeeds, the FPGA design may not timing on a particular device. Not all timing failures are reported as errors, so please check the reports of the place-and-route tools to verify that the hardware met timing.

Regards,
Ralph

Hi Ralph,

Thank you for your reply.
I use co_memory, not co_stream, as CoValidator HDL Testbench Generator can't create testbench with co_memory.
Here is my code in HW process.


other code works well even after generating HDLs, but after I just changed my HW process to the above, it does'nt work, can you please diagnose the hardware design?


Another question, for example I have 3 processes, named A, B, C. The sequence must be A->B->C.
because of some reasons, process B can't implemented using HW, but process A & C can implemented using HW.
so if process A and C are HW process, and B is a SW process, Can Impulse C do it? If it can ,how?
A(sw)->B(sw)->C(sw) Impulse C can
A(hw)->B(hw)->C(hw) Impulse C can
A(hw)->B(sw)->C(hw) Impulse C can??

Hi Robin,

The co_memory_ptr function is not supported in hardware processes, only in software processes. In hardware, you must use co_memory_readblock/co_memory_writeblock, and supply C arrays to store the buffers for those block transfer operations. See the Function Reference section of the Impulse C User Guide.

What were the signs that the design "didn't work" after generating HDL?

All three cases of connecting processes between hardware and software will work, in general. The Impulse C compiler analyzes the connections and generates hardware/software interfaces wherever the stream/memory/etc. crosses a hardware/software boundary, and these interfaces appear in the top-level generated HDL entity (or bus wrapper).

Regards,
Ralph