Greeting all,
I implemented my design in VHDL but i thought i would switch to impulse c if the answers to my question are positive, please any help in getting an answer would be appreciated.

1.

Is it possible to ensure that impulse c will use some of the space saving features. such as implementing a FIFO of arbitrary length in the smart ram (which has pre-built FIFO managers) instead of general ram or logic blocks?

2.

Also does it take advantage of the fact each CLB in the virtex 4 can be a 16 bit shift register and cascaded?

Thank you in advance
Rizgar Mella

Hi,
Impulse C may influence synthesis only through the HDL it generates along with referenced HDL libraries, ultimately it is up to synthesis for implementation details some of which may be controlled via its settings. Impulse C generated HDL is mostly generic except for RAM generation which may be vendor specific (e.g. dual-port RAMs, block vs. distributed RAM, etc.) and the HDL libraries (co_* objects, etc.) also generally do not instantiate low-level primitives. If the user needs to excert finer control over implementation they may do so through the settings of the implementation tool, through the use of #pragma CO IMPLEMENTATION for external user provided primitive functions, and through the HDL libraries used.

Ed

Thank You i will look into that