Help - Search - Members - Calendar
Full Version: APU interface
Impulse Support Forums > Impulse Forums > Xilinx Platform Support
Rock
Hi all,

i am working on ML403 board.I have been trying to run Impulse C programs (just hello world and Adder)with the APU interface but could not find the solution.
whats wrong with this interface. With the PLB both works fine.
What do i need to do.


Please can anyone help...


Thanks in Advance!

Reddy,
etrexel
QUOTE (Rock @ Jun 4 2008, 03:27 AM) *
Hi all,

i am working on ML403 board.I have been trying to run Impulse C programs (just hello world and Adder)with the APU interface but could not find the solution.
whats wrong with this interface. With the PLB both works fine.
What do i need to do.

Please can anyone help...

Thanks in Advance!
Reddy,

Hi,
Please see the tutorials for the Fractal Image Generator which go through the steps when using the APU. The tutorials are located via the CoDeveloper IDE under Help->"Platofrm Support Package Help" and selecting the file "PSP_Xilinx_Virtex_II_Pro.chm". Main points to check:
- clocks: fcb_v10's FCB_CLK must be same as apu_clk of your module and be an integer ratio to the CPU's clock.
- APU is enabled: C_APU_CONTROL of ppc405 is set to "0b0000000000000001" and the MSR is being set (MSR is automatically set in generated co_init.c via mtmsr() funciton)

If this doesn't help, please describe the error you are seeing and post or email to support@impulsec.com your EDK .mhs file.

Ed
Rock
QUOTE (etrexel @ Jun 4 2008, 07:07 PM) *
Hi,
Please see the tutorials for the Fractal Image Generator which go through the steps when using the APU. The tutorials are located via the CoDeveloper IDE under Help->"Platofrm Support Package Help" and selecting the file "PSP_Xilinx_Virtex_II_Pro.chm". Main points to check:
- clocks: fcb_v10's FCB_CLK must be same as apu_clk of your module and be an integer ratio to the CPU's clock.
- APU is enabled: C_APU_CONTROL of ppc405 is set to "0b0000000000000001" and the MSR is being set (MSR is automatically set in generated co_init.c via mtmsr() funciton)

If this doesn't help, please describe the error you are seeing and post or email to support@impulsec.com your EDK .mhs file.

Ed



thanks for the reply!

i will try and let you know...


once again thanks!

Reddy,
Rock
Dear Sir,

i could not able to carry out the Fractal Image Generator program due to lack of LCD display.
So i tried the Tripple DES (for PSP_Xilinx_Virtex_II_Pro)program given in the impusle help. Could not able to talk to FPGA.
I have sent my mhs file to the given email id support@impulsec.com .


thanks in advance.

Reddy


QUOTE (Rock @ Jun 4 2008, 07:12 PM) *
thanks for the reply!

i will try and let you know...
once again thanks!

Reddy,
etrexel
QUOTE (Rock @ Jun 9 2008, 03:43 AM) *
Dear Sir,

i could not able to carry out the Fractal Image Generator program due to lack of LCD display.
So i tried the Tripple DES (for PSP_Xilinx_Virtex_II_Pro)program given in the impusle help. Could not able to talk to FPGA.
I have sent my mhs file to the given email id support@impulsec.com .

thanks in advance.
Reddy

Hi,
I just sent you an updated MHS file with the following line added to ppc405_virtex4:
PARAMETER C_APU_CONTROL = 0b0000000000000001

Without this, the APU interface is disabled and typically results in the CPU appearing to lock up and/or reset whenever an instruction accessing the APU is encountered.

Please try the change and let us know how it goes,
Ed
Rock
QUOTE (etrexel @ Jun 9 2008, 11:06 AM) *
Hi,
I just sent you an updated MHS file with the following line added to ppc405_virtex4:
PARAMETER C_APU_CONTROL = 0b0000000000000001

Without this, the APU interface is disabled and typically results in the CPU appearing to lock up and/or reset whenever an instruction accessing the APU is encountered.

Please try the change and let us know how it goes,
Ed


Hi Sir,

Thanks for the reply.I tried with the added APU_Control Parameter in MHs file,now all my program are working. Actually i was trying to set this in the generated xparamaters file,naturally when i rebuild the software i could not able to find the changes made before.why can't XPS is not generating the required APU_CONTROL = 0b0000000000000001 when we supposed to use this interface. Did i made any mistake. Could you please reply me.


Thanks in Advance!

Reddy,
etrexel
QUOTE (Rock @ Jun 10 2008, 08:15 AM) *
Hi Sir,

Thanks for the reply.I tried with the added APU_Control Parameter in MHs file,now all my program are working. Actually i was trying to set this in the generated xparamaters file,naturally when i rebuild the software i could not able to find the changes made before.why can't XPS is not generating the required APU_CONTROL = 0b0000000000000001 when we supposed to use this interface. Did i made any mistake. Could you please reply me.

Thanks in Advance!

Reddy,

Hi,
The Fractal Image Tutorial contined in "PSP_Xilinx_Virtex_II_Pro.chm" includes the step of adding the APU_CONTROL line to the MHS and all others steps necessary in order to use the APU interface, this is why I had recommended it. In newer versions of EDK v9.x and up, the APU_CONTROL is accessible via right-clicking the 'ppc405_virtex4', choosing "Configure IP", and at the top of the "APU" tab you can enter the register value - default disables the APU and must be changed to "0b0000000000000001".

Ed
Rock
QUOTE (etrexel @ Jun 10 2008, 08:33 AM) *
Hi,
The Fractal Image Tutorial contined in "PSP_Xilinx_Virtex_II_Pro.chm" includes the step of adding the APU_CONTROL line to the MHS and all others steps necessary in order to use the APU interface, this is why I had recommended it. In newer versions of EDK v9.x and up, the APU_CONTROL is accessible via right-clicking the 'ppc405_virtex4', choosing "Configure IP", and at the top of the "APU" tab you can enter the register value - default disables the APU and must be changed to "0b0000000000000001".

Ed


Hi Sir,

Thanks for the help.


Reddy.
This is a "lo-fi" version of our main content. To view the full version with more information, formatting and images, please click here.
Invision Power Board © 2001-2010 Invision Power Services, Inc.