Hi,

I am trying to implement the ImageFilterDMA example and I am having troubles receiving the signal back for co_signal_wait. Is there any constraint in the UCF file or additional specification within the Impulse C program that need to be added for a XUP Virtex II Pro board?

Is it necessary to add the following lines to the UCF file when running on DDR RAM?

INST = "dcm_1/dcm_1/DCM_INST" CLKOUT_PHASE_SHIFT = FIXED"
INST = "dcm_1/dcm_1/DCM_INST" PHASE_SHIFT = 90"

I am having troubles implementing this example in EDK 9.1.
Please help.

Thank you

Hi,
Impulse C will not generally require constraints beyond the normal clock speed settings, what you are describing "should" be contained within one of the reference designs - these are usually the best starting point as they contain all the necessary constraints, etc. to work and then adding Impulse C is usually just a matter of adding the IP and connecting it the appropriate bus. It would be best to first verify correct memory operation (part of the reason you may need the constraints you listed) before running the ImageFilter DMA example - using the PowerPC and/or XMD will help to do a memory test.
If you are not receiving the "done" signal back, it is likely due to the Impulse C process not running to completion - assuming clocks, buses, and memory mappings are all correct, if the DDR memory is on the PLB bus please note that Impulse C presently only use the OPB bus to access memory and would require an opb2plb bridge added to the XPS/EDK project which includes:
1) connecting the opb2plb breidge to the OPB and PLB busses (SDCR not required)
2) connect the "BGI_Trans_Abort" port of the opb2plb and plb2opb together
3) Configuring the opb2plb memory map which at minimum includes:
a) OPB Register Base/High Address, this is where the CPU finds the bridge's registers
b ) Range 0 Base/High Address, this is the address range the bridge will map FROM the OPB bus and forward do memory requests on the PLB bus

Ed

Thank you for your help.