Hi,
I'd like to have some further details about the generate options when generating for the Microblaze/uCLinux platform. In the examples a dual clock is used every time. Is that required or is it also possible to let the peripheral run with the same clock rate?
Another thing I'd like to get explained is the FSL connection in EDK and in the fsl header file. In the examples the fast simplex links are simply connected in order but it is not explained in detail. I have a situation with 5 FSL links where fsl_v20_0 is used for the debug module and 1-4 are added manually. How do I find in which order they have to be connected to which FSL of the processor? Which FSL=X parameter do I have to use in the makefile (I assume 1)?
Could you please give some more details, especially about the restrictions for this platform and general design hints?
As mentioned before I created an application using 4 FSL which connect between two hardware and two software processes. The application starts and the first software process sends something to the first hardware process. Nothing happens for about 3 seconds and then the XMD reports a "pipeline stalled" error.
A smaller test application with 2 FSL connections between 1 hardware and 1 software process worked without problems.
Thanks in advance and best regards
Jarno Radde
Océ Technologies B.V.
