Dear Administrator:
I'm fresh in ImpulseC . In my graduation design , I have to employ ImpulsC to achieve fatigue detection in Altium Nanoboard 2 . Since the WishBone Bus is employed in Altium Platform, I'm puzzled to joint the IP core created by ImpulseC to the soft processors in Altium .
Thanks.

Hi ureyhu,

Glad to know that you chose Impulse C to implement your graduation design. I'm not familiar the the Altium Nanoboard 2 platform and the WishBone Bus, but can give you some general suggestions on how to connect the Impulse-C generated IP Core and the processor.

The main programming model of Impulse C is using co_streams. If you use Altera FPGA, from the Nios II processor's prospective, an ImpulseC module is a memory-mapped slave connected to the data bus. When the processor reads from/writes to a particular address, it actually gets/sends the data from/to a co_stream. If you prefer to use a Xilinx FPGA, the MicroBlaze processor accesses the ImpulseC module via FSL bus. To make this happen, the hardware side needs to have an HDL wrapper to interface the data bus signals and ImpulseC co_stream signals. For a large number of platform like Xilinx and Altera, we provide Platform Support Packages (PSP) to help you do this task automatically. The Altium Nanoboard 2 platform is not supported yet. My guess is that you can utilize the HDL wrapper code generated by our Xilinx/Altera PSP to interface the processor and ImpulseC generated module, but you need to find out a way to let the Altium software tool recognize the IP Core, and make the connection. Please refer to CoDeveloper User Guide for more information. Also you can learn from our existing PSPs in the CoDeveloper installation, as in CoDeveloper3\Architectures.

Hope this helps.

Mei