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[Ezquija]

Hi there,

I'm having problems while using EDK 9.1 and the partial reconfiguration flow proposed by Xilinx to reconfigure some IP cores on my V4XF12 board using the HW/PPC core. As this flow requires an OPB-driven core as the modules to be reconfigured, I need to generate working OPB cores from ImpulseC.

There are couple of issues when Impulsec OPB generated cores are used on latest EDK releases. One of this problem is due to a missing OPB/IPIF core on EDK 9.1. The missing core in question is called opb_ipif_ssp0. This core is being used by the impulsec HDL generated code and seems to be unsupported and removed from EDK due to a change on the way that OPB/IPIF works since EDK 9.1. As a nasty way to workaround this, I copied over the core from a working installation of EDK8.2 (available at /EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_ssp0_v1_00_a directory) to a working installation of EDK9.1. With this, the synth. problems did not appear and the design bitstream can be generated. However the OPB core din't work.

So, I'm wondering if any of you already face this issue before and if you know a way to workaround this. It would be great to have a working design with EDK 9.1 that uses OPB generated cores. At least, a working example of an OPB bus wrapper of the impulsec logic that didn't use the opb_ipif_ssp0 core.

I'm attaching a generated OPB core which is quite simple and reproduces the problem. The link to download the reference code is here.

Thanks in advance,

EZ