1 reply to this topic

[gchow]

The documentation stated that CoValidator currently only support the co_stream interface, is there any plan for supporting the other interfaces, such as co_signal, co_register and co_memory ? If so, is there any projection when these interfaces will be supported.

Finally, given that the current implementation of CoValidator does not support them, what exactly will it mean when a design with say instances of co_register and co_signal is compiled with modelSim testbench generation on. Any tips on how to make things work, or is the amount of work not worth it, you are better off writing your own testbench in those cases (hope not, I was really looking forward to using the CoValidator to simplify my hardware simulation setup).

Thanks in advance,
Gloria

[RalphBodenner]

Hi Gloria,

We do plan to support the other interfaces, but there's no planned release date yet. The next revision will likely add the creation of trace files during desktop simulation for register and signal interfaces. Producing accurate HDL testbenches for these interfaces is somewhat difficult, due to their unsynchronized nature.

Limitations of the current version of CoValidator can be worked around by editing the generated HDL testbench. Register, signal, and memory ports are left unconnected in the testbench, so you can add stimulus code for those interfaces.

Ralph