1 reply to this topic

[Juanma Gomez]

Hi, I'm new to Impulse C and I'm developing a simple Hello World core, and using it on a a EDK proyect.

The Core is as easy as this:

void ImgInverter(co_stream Orig, co_stream Inv)
{
co_uint8 nSample, InvSample;
do { // Hardware processes run forever

co_stream_open(Orig, O_RDONLY, UINT_TYPE(STREAMWIDTH));
co_stream_open(Inv, O_WRONLY, UINT_TYPE(STREAMWIDTH));

while ( co_stream_read(Orig, &nSample, sizeof(co_uint8)) == co_err_none ) {
#pragma CO PIPELINE
InvSample = 255 - nSample;
co_stream_write(Inv, &InvSample, sizeof(co_uint8));
}
co_stream_close(Orig);
co_stream_close(Inv);
} while(1);
}

I'm generating this for an FSL interface, first I test it on an Microblaze based project whitout problem (I've allready do the software simulation without problem) except the low speed.

But when I test it on my project using it at high speed (either simulating with modelsim) the core is unable to throw 1 data/cycle.

Here is what stage master says:
Block Type: Pipeline
Latency: 2
Rate: 1 cycles/result
Max. Unit Delay: 8
Effective Rate: 8

When I test it on my project with direct conect to my vhdl producer, it throws 1 data/ 4 cyles after the latency




and when I simulate with Modelsim It look like the Pipeline is not working well.



I don't know how to make it works.

Please any info or help?

[RalphBodenner]

Hi Juanma,

The 'clk' signal in the ModelSim shot is running at a different rate than 'sclk'... did you generate the design with dual clocks? The 'sclk' input is unused (left open) by default.

If the input comes in every clock cycle, the output should also issue new output each clock (after an initial latency to fill the pipeline).

Ralph