10 replies to this topic

[zje]

I'm trying to do a very simple example of impulseC from scratch. I made a HW process in CoDeveloper and tested it fine.
I then tried to write the software in EDK and I'm running into big troubles. I don't think I really understand how the HW/SW interface works. My process takes in two 32bit inputs and the returns the output, 32 bits. The hardware process is called "mult." I have successfully imported the pcore and connected it. Running a hello world without and impulse functions on the hardware doesn't blow up, so at least I know it's not totally wrong. I don't know if I'll run into hardware issues yet, but I'm stuck on software.

CODE

#include "xio.h"
#include "xparameters.h"
#include "co.h"
#include "mult.h"
#include "fsl_if.h"

Xint32 a,b,c;
unsigned long err;

int main() {
    co_architecture my_arch;
    void *param = NULL;
    my_arch = co_initialize(param);
    co_execute(my_arch);
    return;
}


void mult(co_stream numIn, co stream result) {
    a = 24;
    b = 24;
    xil_printf("Hello World\r\n");
    xil_printf("Multiplying %d by %d\r\n");
    HW_STREAM_OPEN(mult, numIn, O_WRONLY, INT_TYPE(STREAMWIDTH));
    HW_STREAM_OPEN(mult, result, O_RDONLY, INT_TYPE(STREAMWIDTH));
    HW_STREAM_WRITE(mult, numIn, a);
    HW_STREAM_WRITE(mult, numIn, b);
    HW_STREAM_READ(mult, result, c, err);
    xil_printf("Result: %d", c);
    HW_STREAM_CLOSE(mult,numIn);
    HW_STREAM_CLOSE(mult,result);
}

Here are the error messages:

CODE

/cygdrive/e/ECASP/mult_impulse/main.c: In function 'main':
/cygdrive/e/ECASP/mult_impulse/main.c:13: warning: assignment makes pointer from integer without a cast
/cygdrive/e/ECASP/mult_impulse/main.c: At top level:
/cygdrive/e/ECASP/mult_impulse/main.c:19: error: expected declaration specifiers or '...' before 'co'
/cygdrive/e/ECASP/mult_impulse/main.c:19: error: conflicting types for 'mult'
/cygdrive/e/ECASP/mult_impulse/mult.h:13: error: previous declaration of 'mult' was here
/cygdrive/e/ECASP/mult_impulse/main.c: In function 'mult':
/cygdrive/e/ECASP/mult_impulse/main.c:26: error: expected ':' or ')' before 'p_mult_numIn'
/cygdrive/e/ECASP/mult_impulse/main.c:27: error: expected ':' or ')' before 'p_mult_numIn'
/cygdrive/e/ECASP/mult_impulse/main.c:28: error: expected ':' or ')' before 'p_mult_result'
/cygdrive/e/ECASP/mult_impulse/main.c:30: error: expected ':' or ')' before 'p_mult_numIn'
/cygdrive/e/ECASP/mult_impulse/main.c:31: error: expected ':' or ')' before 'p_mult_result'

Any insight would be very appreciated. I've been working at this for a while, but completely lost.
I have read most of "Practical FPGA Programming in C," but it doesn't seem to be helping me with my problems. I'm not quite sure of how to use the HW_STREAM_XXXX macros correctly and I can't find any documentation on them...

Thanks!

[meix]

Hello zje,

First, please make sure that you added all the necessary source and header files to the EDK software project. Is the "co_init.c" in the project?

It seems like there is some co_stream name mismatch between hardware and software. Can you please send the whole Impulse C project for a diagnosis, including the *_hw.c and mult.h?

Thanks,

Mei

I'm trying to do a very simple example of impulseC from scratch. I made a HW process in CoDeveloper and tested it fine.
I then tried to write the software in EDK and I'm running into big troubles. I don't think I really understand how the HW/SW interface works. My process takes in two 32bit inputs and the returns the output, 32 bits. The hardware process is called "mult." I have successfully imported the pcore and connected it. Running a hello world without and impulse functions on the hardware doesn't blow up, so at least I know it's not totally wrong. I don't know if I'll run into hardware issues yet, but I'm stuck on software.

CODE

#include "xio.h"
#include "xparameters.h"
#include "co.h"
#include "mult.h"
#include "fsl_if.h"

Xint32 a,b,c;
unsigned long err;

int main() {
    co_architecture my_arch;
    void *param = NULL;
    my_arch = co_initialize(param);
    co_execute(my_arch);
    return;
}


void mult(co_stream numIn, co stream result) {
    a = 24;
    b = 24;
    xil_printf("Hello World\r\n");
    xil_printf("Multiplying %d by %d\r\n");
    HW_STREAM_OPEN(mult, numIn, O_WRONLY, INT_TYPE(STREAMWIDTH));
    HW_STREAM_OPEN(mult, result, O_RDONLY, INT_TYPE(STREAMWIDTH));
    HW_STREAM_WRITE(mult, numIn, a);
    HW_STREAM_WRITE(mult, numIn, b);
    HW_STREAM_READ(mult, result, c, err);
    xil_printf("Result: %d", c);
    HW_STREAM_CLOSE(mult,numIn);
    HW_STREAM_CLOSE(mult,result);
}

Here are the error messages:

CODE

/cygdrive/e/ECASP/mult_impulse/main.c: In function 'main':
/cygdrive/e/ECASP/mult_impulse/main.c:13: warning: assignment makes pointer from integer without a cast
/cygdrive/e/ECASP/mult_impulse/main.c: At top level:
/cygdrive/e/ECASP/mult_impulse/main.c:19: error: expected declaration specifiers or '...' before 'co'
/cygdrive/e/ECASP/mult_impulse/main.c:19: error: conflicting types for 'mult'
/cygdrive/e/ECASP/mult_impulse/mult.h:13: error: previous declaration of 'mult' was here
/cygdrive/e/ECASP/mult_impulse/main.c: In function 'mult':
/cygdrive/e/ECASP/mult_impulse/main.c:26: error: expected ':' or ')' before 'p_mult_numIn'
/cygdrive/e/ECASP/mult_impulse/main.c:27: error: expected ':' or ')' before 'p_mult_numIn'
/cygdrive/e/ECASP/mult_impulse/main.c:28: error: expected ':' or ')' before 'p_mult_result'
/cygdrive/e/ECASP/mult_impulse/main.c:30: error: expected ':' or ')' before 'p_mult_numIn'
/cygdrive/e/ECASP/mult_impulse/main.c:31: error: expected ':' or ')' before 'p_mult_result'

Any insight would be very appreciated. I've been working at this for a while, but completely lost.
I have read most of "Practical FPGA Programming in C," but it doesn't seem to be helping me with my problems. I'm not quite sure of how to use the HW_STREAM_XXXX macros correctly and I can't find any documentation on them...

Thanks!

[zje]

Yes, the co_init.c file is included in the sources folder.

Project File
I couldn't for the life of me figure out how to attach a file, so I uploaded to a slow web server.
Sorry, this is just not my week

Hello zje,

First, please make sure that you added all the necessary source and header files to the EDK software project. Is the "co_init.c" in the project?

It seems like there is some co_stream name mismatch between hardware and software. Can you please send the whole Impulse C project for a diagnosis, including the *_hw.c and mult.h?

Thanks,

Mei

[meix]

Hi zje,

I looked at your project files, and found some problem with name mismatch. In "mult_sw.c", there are two processes, "Producer" and "Consumer". The co_stream in a process will be given a name in generated HDL containing the process name. Please see the following component from the top level HDL file "fsl_mult_arch.vhd":

component mult_arch is
port (
reset : in std_ulogic;
sclk : in std_ulogic;
clk : in std_ulogic;
p_Producer_numIn_en : in std_ulogic;
p_Producer_numIn_eos : in std_ulogic;
p_Producer_numIn_data : in std_ulogic_vector (31 downto 0);
p_Producer_numIn_rdy : out std_ulogic;
p_Consumer_result_en : in std_ulogic;
p_Consumer_result_data : out std_ulogic_vector (31 downto 0);
p_Consumer_result_eos : out std_ulogic;
p_Consumer_result_rdy : out std_ulogic
);
end component;

Therefore, in the software code you rewrote for the EDK, if you use HW_STREAM macros, at least you need to keep the same process name.

HW_STREAM_WRITE(Producer, numIn, a);
HW_STREAM_WRITE(Producer, numIn, b);
HW_STREAM_READ(Consumer, result, c, err);
xil_printf("Result: %d", c);
HW_STREAM_CLOSE(Producer,numIn);
HW_STREAM_CLOSE(Consumer,result);

This way, the hardware and software interface can be connected properly.

Let me know if you find other problems.

Regards,

Mei

[meix]

There is one more thing that causes problems. In the automatically generated "co_init.c", the process names "Producer" and "Consumer" are present. Please use the same names in the code you wrote for EDK. Otherwise, the process name won't be recognized and this will cause errors. Actually, you can use the "mult_sw.c" in your EDK project, using macros to distinguish between simulation and EDK execution. You can have something like this:

#ifdef IMPULSE_C_TARGET
#include "xio.h"
#include "xparameters.h"
#endif

#ifdef IMPULSE_C_TARGET
HW_STREAM_WRITE(Producer, numIn, a);
#else
co_stream_write(Producer, &testValue, sizeof(co_int32));
#endif

Hope this helps.

Mei

[zje]

Cool! Thank you so much, that was very helpful for understanding how this actually works.

I'm still having some troubles, but I want to try and see if I can figure it out before posting.

[zje]

Here is my code now:

CODE

#include "xio.h"
#include "xparameters.h"
#include "co.h"
#include "mult.h"
#include "fsl_if.h"

Xint32 a,b,c;
unsigned long err;

int main() {
    co_architecture my_arch;
    void *param = NULL;
    my_arch = co_initialize(param);
    co_execute(my_arch);
    xil_printf("In main\r\n");
    return;
}


void Producer(co_stream numIn) {
    xil_printf("Entered Producer\r\n");
    a = 24;
    b = 24;
    HW_STREAM_WRITE(Producer, numIn, a);
    HW_STREAM_WRITE(Producer, numIn, b);
    xil_printf("Multiplying %d by %d\r\n",a,b);
    HW_STREAM_CLOSE(Producer,numIn);
}

void Consumer(co_stream result) {
    xil_printf("Entered Consumer\r\n");
    HW_STREAM_OPEN(Consumer, result, O_RDONLY, INT_TYPE(STREAMWIDTH));
    xil_printf("Opened Consumer\r\n");
    HW_STREAM_READ(Consumer, result, c, err);
    xil_printf("Result: %d\r\n", c);
    //HW_STREAM_READ(Consumer, result, c, err);
    HW_STREAM_CLOSE(Consumer,result);
}

It seems to be waiting on the read, the output is:
Entered Producer
Multiplying 24 by 24
Entered Consumer
Opened Consumer

Adding the second dummy read (currently commented out) didn't alleviate the problem.
I also went back to the HW and changed the streamdepth to 1 for the result stream.
If I do a nonblocking read, it just returns 0.

Thanks!

[meix]

Hi zje,

The software code for EDK looks fine to me. Probably something went wrong in the EDK project? For example, did you use a separate clock for the Impulse C IP core? What is the platform that you run the test project? I may need more information for further diagnosis...

Regards,

Mei

[zje]

I use the system clock for the IP core... is that bad? I figured that since I am only using a multiplier, it runs fast enough (the project synthesizes without any timing warnings) so that I don't need a separate clock. Should I use a separate clock even though the IP core can technically run at the system clock speeds?

I am testing the platform on a Spartan 3E Starter Board, Revision D:
http://www.digilentinc.com/Products/Detail...p;Prod=S3EBOARD

Thanks for your reply!

[meix]

I never used the Digilent Spartan 3E board before, but I assume it would be similar to the Xilinx boards.

Is the test application "TestApp_Memory" or "TestApp_Peripheral" working with no problem? Are the FSL ports connected as in the MicroBlaze tutorial? Please try to use a separate lower clock rate for the Impulse IP core to try if it works. Say, if your system clock rate is 100 MHz, try 50 MHz.

Hope this helps.

Mei

[zje]

Thanks so much for the insight.
I just compared my FSL connections to the ones in the tutorial and they were wrong.

Sorry for all the trouble and thank you very much for your help!