1 reply to this topic

[The.Soloist]

Hi,

I'm trying out the example of ExtFunction, and I'm wondering if there's a way to pass a number from Impulse C function to the external VHDL's "generic" parameter part. i.e.:

CODE

library IEEE;
use IEEE.std_logic_1164.all;

entity add_g is
  generic(left : natural := 31;         -- top bit
          prop : time := 100 ps);
    port (a    : in  std_logic_vector (left downto 0);
          b    : in  std_logic_vector (left downto 0);
          cin  : in  std_logic;
          sum  : out std_logic_vector (left downto 0);
          cout : out std_logic);
end entity add_g;

architecture behavior of add_g is
begin  -- behavior
  adder: process
           variable carry : std_logic; -- internal
           variable isum : std_logic_vector(left downto 0);  -- internal
         begin
           carry := cin;
           for i in 0 to left loop
             isum(i) := a(i) xor b(i) xor carry;
             carry  := (a(i) and b(i)) or (a(i) and carry) or (b(i) and carry);
           end loop;
           sum  <= isum;
           cout <= carry;
           wait for prop;   -- signals updated after prop delay
         end process adder;
end architecture behavior;  -- of add_g

I want to pass a number to "left" or "prop", used as a parameter in the architecture part. Is that possible? Or do I have to add ports to implement this?

Thanks

[RalphBodenner]

Yes, you'll have to use a port/variable to do this instead of using a generic.