1 reply to this topic

[Jonathan]

My application receives a buffer filled with variable length messages that I would like to process in parallel. Because the messages are variable length, I don't know the starting position of the second message until I look at the beginning of the first message. Therefore, if I were to loop through the block, setting a new start index, this would cause a side-effect that would preclude the loop from being unrolled. I could simply loop through in a pre-process stage to find the starting position of each message in a fairly short number of operations, but I was wondering if it would be possible to automatically offset my pipelines from one another so that after the first pipeline calculates the position of the second message, it triggers the second pipeline to start. Now, since everything is offset, it also saves me from a few concurrency issues I was going to have...

What is the most efficient method to do this offsetting in Impulse C? Must I declare a macro and call it recursively, or is there some way for me to allow for a tiny amount of side-effects up to some point in a loop, and then the pipelining offsets from that point on? I.E.

for (int32 i = 0; i < MAX && next <= buffer_size; i++ ) {
#pragma CO PIPELINE
#pragma CO BEGIN_SIDE_EFFECTS
offset = next_offset;
next_offset += buffer[offset];
#pragma CO END_SIDE_EFFECTS
// Now, each pipeline is offset by a cycle or two to allow the previous code to initialize it...
}

Of course, I'm completely new to FPGAs and Impulse C, so if offsetting pipelines from each other is a bad idea, please let me know how I should be approaching this problem...

Thanks!
Jonathan

[RalphBodenner]

Hi Jonathan,

I'd first try precalculating the offsets to remove a dependency in the pipelined loop. You can use Stage Master Explorer to compare the two variations (calculate offsets in advance, or in the loop) and see how the pipeline rate is affected.

Regards,
Ralph