1 reply to this topic

[qingfeng]

when i generate the hdl file, a error shows to me:======== Building target 'build' in file _Makefile ========
HW_SRC="EdgeDetect_hw.c"; \
for i in $HW_SRC; do CPP_INCLUDES="$CPP_INCLUDES -include $i"; done; \
echo | "D:/Program Files/impulse/CoDeveloper3/MinGW/bin/gcc" -E -DIMPULSE_C_SYNTHESIS -DRC_INVOKED -DBYTE="unsigned char" -DWORD="unsigned short" -DDWORD="unsigned int" -Dsize_t="long unsigned int" -DNULL=0 -Dstdin=NULL "-ID:\Program Files\impulse\CoDeveloper3\Include" "-ID:/Program Files/impulse/CoDeveloper3/StageMaster/include" $CPP_INCLUDES - > EdgeDetect.i
"D:/Program Files/impulse/CoDeveloper3/bin/impulse_snoot" -Timpulse-c EdgeDetect.i EdgeDetect.snt
"D:/Program Files/impulse/CoDeveloper3/bin/impulse_prep" EdgeDetect.snt EdgeDetect.pk0
Impulse C Transformations
Copyright 2002-2007, Impulse Accelerated Technologies, Inc.
All rights reserved.
Build Feb 23 2008.
processing EdgeDetect.snt...
"D:/Program Files/impulse/CoDeveloper3/bin/impulse_porky" -iterate -fold -unused-syms -unused-types -Dmemcpys EdgeDetect.pk0 EdgeDetect.pk1
"D:/Program Files/impulse/CoDeveloper3/bin/impulse_porky" -build-arefs EdgeDetect.pk1 EdgeDetect.pky
"D:/Program Files/impulse/CoDeveloper3/bin/impulse_impc" EdgeDetect.pky EdgeDetect.sic
Impulse C Preprocessor
Copyright 2003-2007, Impulse Accelerated Technologies, Inc.
All rights reserved.
Build Feb 23 2008.
---Software activated---
processing EdgeDetect.pky...
analyzing co_initialize...
found architecture definition: edge_detect_arch/Generic_VHDL
analyzing config_edge_detect...
creating stream blue_source_pixeldata ...
creating stream green_source_pixeldata ...
creating stream red_source_pixeldata ...
creating stream blue_result_pixeldata ...
creating stream green_result_pixeldata ...
creating stream red_result_pixeldata ...
creating signal header_ready ...
creating process producer_process ...
creating process blue_process ...
creating process green_process ...
creating process red_process ...
creating process consumer_process ...
"D:/Program Files/impulse/CoDeveloper3/bin/impulse_s2xml" EdgeDetect.sic > EdgeDetect.xic
Impulse C to XML
Copyright 2003-2007, Impulse Accelerated Technologies, Inc.
All rights reserved.
Build Feb 23 2008.
"D:/Program Files/impulse/CoDeveloper3/StageMaster/bin/impulse_sm" -g "-aD:/Program Files/impulse/CoDeveloper3/Architectures/generic.xml" -hhw EdgeDetect.xic EdgeDetect.xhw
Stage Master Version 3.0
Copyright by Green Mountain Computing Systems, 2003-2008.
All rights reserved.
Build Feb 19 2008.
Analyzing edge_detect:
...................................................................... done 70 blocks
Generating . done
Results:
|----------------------------------------
| edge_detect
|----------------------------------------
| Block #0:
| Stages: 1
| Max. Unit Delay: 0
| Block #1 loop:
| Stages: 63
| Max. Unit Delay: 0
| Block #2 loop:
| Stages: 3
| Max. Unit Delay: 33
| Block #3:
| Stages: 1
| Max. Unit Delay: 0
| Block #4 loop:
| Stages: 2
| Max. Unit Delay: 33
| Block #5:
| Stages: 1| Max. Unit Delay: 0
| Block #6 loop:
| Stages: 49
| Max. Unit Delay: 33
| Block #7:
| Stages: 1
| Max. Unit Delay: 0
| Block #8:
| Stages: 1
| Max. Unit Delay: 33
| Block #9:
| Stages: 1
| Max. Unit Delay: 0
| Block #10:
| Stages: 1
| Max. Unit Delay: 33| Block #11:
| Stages: 1| Max. Unit Delay: 32
| Block #12:
| Stages: 1
| Max. Unit Delay: 32
| Block #13:
| Stages: 2
| Max. Unit Delay: 33
| Block #14:| Stages: 1
| Max. Unit Delay: 32
| Block #15:
| Stages: 1
| Max. Unit Delay: 32
| Block #16:
| Stages: 2
| Max. Unit Delay: 33
| Block #17:
| Stages: 1
| Max. Unit Delay: 32
| Block #18:
| Stages: 1
| Max. Unit Delay: 32
| Block #19:
| Stages: 2
| Max. Unit Delay: 33
| Block #20:
| Stages: 1
| Max. Unit Delay: 32
| Block #21:
| Stages: 1
| Max. Unit Delay: 32
| Block #22:
| Stages: 2
| Max. Unit Delay: 33
| Block #23:
| Stages: 1
| Max. Unit Delay: 32
| Block #24:
| Stages: 1
| Max. Unit Delay: 32
| Block #25:
| Stages: 2
| Max. Unit Delay: 33
| Block #26:
| Stages: 1
| Max. Unit Delay: 32
| Block #27:
| Stages: 1
| Max. Unit Delay: 32
| Block #28:
| Stages: 2
| Max. Unit Delay: 33
| Block #29:
| Stages: 1
| Max. Unit Delay: 32
| Block #30:
| Stages: 1
| Max. Unit Delay: 32
| Block #31:
| Stages: 2
| Max. Unit Delay: 33
| Block #32:
| Stages: 1
| Max. Unit Delay: 32
| Block #33:
| Stages: 1
| Max. Unit Delay: 32
| Block #34:
| Stages: 2
| Max. Unit Delay: 33
| Block #35:
| Stages: 1
| Max. Unit Delay: 64
| Block #36:
| Stages: 1
| Max. Unit Delay: 32
| Block #37:
| Stages: 1
| Max. Unit Delay: 33
| Block #38:
| Stages: 1
| Max. Unit Delay: 64
| Block #39:
| Stages: 1
| Max. Unit Delay: 32
| Block #40:
| Stages: 1
| Max. Unit Delay: 33
| Block #41:
| Stages: 1
| Max. Unit Delay: 64| Block #42:
| Stages: 1| Max. Unit Delay: 32
| Block #43:
| Stages: 1
| Max. Unit Delay: 33
| Block #44:
| Stages: 1
| Max. Unit Delay: 64
| Block #45:| Stages: 1
| Max. Unit Delay: 32
| Block #46:
| Stages: 1
| Max. Unit Delay: 1
| Block #47:
| Stages: 1
| Max. Unit Delay: 0
| Block #48:
| Stages: 1
| Max. Unit Delay: 0
| Block #49:
| Stages: 1
| Max. Unit Delay: 1
| Block #50:
| Stages: 1
| Max. Unit Delay: 0
| Block #51:
| Stages: 1
| Max. Unit Delay: 0
| Block #52:
| Stages: 1
| Max. Unit Delay: 1| Block #53:
| Stages: 1| Max. Unit Delay: 1
| Block #54:
| Stages: 1
| Max. Unit Delay: 0
| Block #55:
| Stages: 1
| Max. Unit Delay: 0
| Block #56:
| Stages: 1
| Max. Unit Delay: 0
| Block #57:
| Stages: 1
| Max. Unit Delay: 1
| Block #58:
| Stages: 1
| Max. Unit Delay: 0
| Block #59:
| Stages: 1
| Max. Unit Delay: 0
| Block #60:
| Stages: 1
| Max. Unit Delay: 0
| Block #61:
| Stages: 1
| Max. Unit Delay: 1
| Block #62:
| Stages: 1
| Max. Unit Delay: 0
| Block #63:
| Stages: 1
| Max. Unit Delay: 0
| Block #64:
| Stages: 1
| Max. Unit Delay: 0
| Block #65 loop:
| Stages: 4
| Max. Unit Delay: 33
| Block #66:
| Stages: 1
| Max. Unit Delay: 0
| Block #67:
| Stages: 1
| Max. Unit Delay: 33
| Block #68:
| Stages: 1
| Max. Unit Delay: 0
| Block #69:
| Stages: 1
| Max. Unit Delay: 0
|----------------------------------------
| Operators:
| 46 Adder(s)/Subtractor(s) (32 bit)
| 2 Comparator(s) (2 bit)
| 1 Comparator(s) (8 bit)
| 5 Comparator(s) (16 bit)
| 18 Comparator(s) (32 bit)
|----------------------------------------
| Total Stages: 84
| Max. Unit Delay: 64
| Estimated DSPs: 0
|----------------------------------------
Writing output ... done
"D:/Program Files/impulse/CoDeveloper3/bin/impulse_arch" "-aD:/Program Files/impulse/CoDeveloper3/Architectures/generic.xml" -dc -swdirsw -files "EdgeDetect_comp.vhd EdgeDetect_top.vhd " EdgeDetect.xic hw/EdgeDetect_top.vhd
Impulse C HDL Design Generator
Copyright 2002-2007, Impulse Accelerated Technologies, Inc.
All rights reserved.
Loading D:/Program Files/impulse/CoDeveloper3/Architectures/generic.xml ...
Loading D:/Program Files/impulse/CoDeveloper3/Architectures/VHDL/Generic/Generic/bus.xml ...
Loading D:/Program Files/impulse/CoDeveloper3/Architectures/VHDL/target.xml ...
Loading D:/Program Files/impulse/CoDeveloper3/Architectures/VHDL/Generic/technology.xml ...
Loading D:/Program Files/impulse/CoDeveloper3/Architectures/VHDL/Generic/Generic/system.xml ...
Loading EdgeDetect.xic ...
"D:/Program Files/impulse/CoDeveloper3/bin/impulse_genvhdl.exe" EdgeDetect.xhw hw/EdgeDetect_comp.vhd
Impulse C RTL Component Generator
Copyright 2002-2007, Impulse Accelerated Technologies, Inc.
All rights reserved.
Generating edge_detect ...
---Output limited to 3000 lines---
---Software activated---
chmod -R +rw hw
Usage: chmod [-Rfh] [ugoa][+-=][rwxXstugoAHS] file ...
make: *** [hardware] Error 1


what does this means? how to work it out?
thanks

[RalphBodenner]

Hi,

This is the error:

chmod -R +rw hw
Usage: chmod [-Rfh] [ugoa][+-=][rwxXstugoAHS] file ...
make: *** [hardware] Error 1

Where the 'chmod' program being run is not the 'chmod' that ships with CoDeveloper. Please make sure that the "%IMPULSEC_HOME%\bin" entry in your PATH environment variable comes before any other directory where a 'chmod' program is installed (for example, a Cygwin directory).

Regards,
Ralph