Here is my loop:
CODE
for(i=0; i<8; i++) {
#pragma CO UNROLL
w[i*2] = SWEND((co_uint32)nSample[i]);
w[i*2+1] = SWEND((co_uint32)(nSample[i]>>32));
}
#pragma CO UNROLL
w[i*2] = SWEND((co_uint32)nSample[i]);
w[i*2+1] = SWEND((co_uint32)(nSample[i]>>32));
}
When I try to generate HDL, I get this error:
CODE
Assertion failure in file "..\transform.cc" at line 655:
test_hw.c:62: Unroll pragma found on malformed loop
make: *** [TEST.pk0] Error 1
test_hw.c:62: Unroll pragma found on malformed loop
make: *** [TEST.pk0] Error 1
I actually tried an empty loop and that didn't work...
FYI, SWEND is defined as:
CODE
#define SWEND(i) ((i&0xff)<<24)|((i&0xff00)<<8)|((i&0xff0000)>>8)|((i>>24)&0xff)
As a side note, I accomplished this in VHDL by connecting signals. I'm going to assume that there's little hope this will compile to do so and will end up doing all the bit masking and ORing... is there a way to some sort of wire mapping type stuff in impulse?
Thanks!












