5 replies to this topic

[ekinzhou]

 2.JPG (143.8K)
Number of downloads: 10

As you can see in the picture, I do not set _rd for in1 and in2, it is automatical set.

I have set the data of in1 and in2, but the result of out is 64'hhhhhhhh...

why? Do I set some signal wrong?

According to this picture, could you tell me if there are something setting wrong? Or how to set them for just one success setting for example.


My purpose, in impulse C, just get the output value, while output= in1 * in2, and the in1 and in2 I give is -1.25 and 2.75 double type respectively. The VHDL file is xilinx generic VHDL file.

Thanks.

[etrexel]

 2.JPG (143.8K)
Number of downloads: 10

As you can see in the picture, I do not set _rd for in1 and in2, it is automatical set.

I have set the data of in1 and in2, but the result of out is 64'hhhhhhhh...

why? Do I set some signal wrong?

According to this picture, could you tell me if there are something setting wrong? Or how to set them for just one success setting for example.


My purpose, in impulse C, just get the output value, while output= in1 * in2, and the in1 and in2 I give is -1.25 and 2.75 double type respectively. The VHDL file is xilinx generic VHDL file.

Thanks.

Hi,
Correct, the '_rdy signals are outputs being driven by the internal logic and you only need to drive the inputs in your test bench. Looking at the picture, the first thing that is incorrect is that the reset signal - reset is active high and typically you will see it be a '1' from 0ns to at least 100ns. Your clock signal 'clk' is also incorrect, just drive 'clk' and 'sclk' with the same clock signal. Fixing these two things you should see some changes. Also, if you want to see the output data coming out on p_consumer_out_data as soon as it is available, just set p_consumer_out_en to '1' and the output data will be valid each time you see p_consumer_out_rdy become a '1'.

Ed

[ekinzhou]

 1.JPG (141.67K)
Number of downloads: 5

Hi,
Correct, the '_rdy signals are outputs being driven by the internal logic and you only need to drive the inputs in your test bench. Looking at the picture, the first thing that is incorrect is that the reset signal - reset is active high and typically you will see it be a '1' from 0ns to at least 100ns. Your clock signal 'clk' is also incorrect, just drive 'clk' and 'sclk' with the same clock signal. Fixing these two things you should see some changes. Also, if you want to see the output data coming out on p_consumer_out_data as soon as it is available, just set p_consumer_out_en to '1' and the output data will be valid each time you see p_consumer_out_rdy become a '1'.

Ed

Thanks, but when I set the reset signal from 0ns to 100ns, I find an error as the new picture showed

[etrexel]

 1.JPG (141.67K)
Number of downloads: 5


Thanks, but when I set the reset signal from 0ns to 100ns, I find an error as the new picture showed

Hi,
To avoid the error, wait until after 100ns before changing any of your input signals.

Ed

[ekinzhou]

Hi,
To avoid the error, wait until after 100ns before changing any of your input signals.

Ed

I have sent the email to support for a few questions. Could you reply me today?

[etrexel]

I have sent the email to support for a few questions. Could you reply me today?

Hi,
Just did.
Ed