2 replies to this topic

[ekinzhou]

I use two input and one output in test bench as the model of impulse C.
When I follow Mr.Ralph Bodenner's advice,
- Set *_eos low
- Put the data on *_data
- Set *_en high
- When *_rdy goes high, the stream will consume the data
- Set *_en low

at set the rdy goes high, I have the problem as below.

[attachment=94:tt.JPG]

[etrexel]

I use two input and one output in test bench as the model of impulse C.
When I follow Mr.Ralph Bodenner's advice,
- Set *_eos low
- Put the data on *_data
- Set *_en high
- When *_rdy goes high, the stream will consume the data
- Set *_en low

at set the rdy goes high, I have the problem as below.

[attachment=94:tt.JPG]

Hi,
This error is most likely due to the '_rdy signal being driven by the HDL by the co_stream which is an output. Please note the last step of setting '_en low is not required if you are supplying data on every cycle. The basic rule for a stream interface is: When BOTH '_en and '_rdy are '1' on the rising edge of the clock, data is transferred.

Ed

[ekinzhou]

Thanks.
I found maybe I misunderstand the signal.
According to the book,
Streams Used in Write Mode
<stream_name>_rdy : OUT -- Ready to accept data.
<stream_name>_en : IN -- Enable write.
<stream_name>_eos: IN -- Write is EOS.
<stream_name>_data: IN -- Write data.
Yes, there is nothing wrong with my HDL files.

Q1 And the _rdy is output I can not set, am I right?

So it must be something wrong with simulation or the wave I set.

Q2 If _rdy is output, how can I set BOTH '_en and '_rdy are '1' ?