13 replies to this topic

[Rock]

Hi all,
Hardware is not processing the encryption algorithm, with the APU interface
My Co-developer Version 3.10,
EDK 10.1,

..................................
output
...................................
Impulse C 3DES DEMO
Running encryption test on FPGA ...
FPGA processing done (1495356 ticks).
FPGA block out: D7 D7 D7 D7 D7 D7 D7 D7
Running encryption test on CPU ...
CPU processing done (9232075 ticks).
CPU block out: AD 6E 29 15 92 57 C5 FB

Any help!!!


thanks

Reddy

[Rock]

In the standalone environment. i have added OPB_timer although PPC has got its own.

[etrexel]

In the standalone environment. i have added OPB_timer although PPC has got its own.

Hi,
Just to make sure: You are running the example as-is in standalone mode and not under Linux or any other OS correct?
And how are you clocks connected within the design?

Ed

[Rock]

Hi,
Just to make sure: You are running the example as-is in standalone mode and not under Linux or any other OS correct?
And how are you clocks connected within the design?

Ed

Hi Sir,
I made clk connections as shown below

for apu_des_0 ip core
apu_clk is connected to sys_clk_s,

fcb_v10_0
SYS_RST---sys_bus_reset,
FCB_CLK---sys_clk_s.

thanks,

[Rock]

Hi Sir,
I made clk connections as shown below

for apu_des_0 ip core
apu_clk is connected to sys_clk_s,

fcb_v10_0
SYS_RST---sys_bus_reset,
FCB_CLK---sys_clk_s.

thanks,

Program running in the standalone environemnt

[etrexel]

Program running in the standalone environemnt

Hi,
And what clock frequencies are being used for the CPU, APU, etc.?

Ed

[Rock]

Hi,
And what clock frequencies are being used for the CPU, APU, etc.?

Ed

Processor clock frequency: 100.00 MHz
Bus clock frequency: 50.00 MHz

[etrexel]

Processor clock frequency: 100.00 MHz
Bus clock frequency: 50.00 MHz

Hi,
The APU is very touchy about 32-bit word alignment but without any complaints. This example wasn't originally written for the APU so please check to ensure all pointers used by an API read and write functions in the software are 32-bit aligned. Simply printing out the pointer's value using "printf("%p",pointer);" and ensure that the two LSb's are both 0's. If you need to ensure alignement for an array, variable, etc. you can do so using a declaration similar to:

int MyVar __attribute__ ((aligned (4))) = 0;

Note that alignment works on global and local static variables only, and it does not work on stack variables.
Ed

[Rock]

Hi,
I have modified the streams for 32 bit data trasfer.
hardware is processing but getting incorrect output.

The below is the output on the Hyperterminal in the standalone environment,

Impulse C 3DES DEMO
Running encryption test on FPGA ...
FPGA block out: 02 c9 83 d7 00 00 bf 54
Running encryption test on CPU ...
CPU block out: ad 6e 29 15 92 57 c5 fb

I have attched 3DES modified code for 32 bit compatible bus,

Any help would be appreciated...

Thanks,

Attached File(s)

•  des_sw.txt (14.22K)
  Number of downloads: 5
•  des_hw.txt (7.92K)
  Number of downloads: 2

[etrexel]

Hi,
I have modified the streams for 32 bit data trasfer.
hardware is processing but getting incorrect output.

The below is the output on the Hyperterminal in the standalone environment,

Impulse C 3DES DEMO
Running encryption test on FPGA ...
FPGA block out: 02 c9 83 d7 00 00 bf 54
Running encryption test on CPU ...
CPU block out: ad 6e 29 15 92 57 c5 fb

I have attched 3DES modified code for 32 bit compatible bus,

Any help would be appreciated...

Thanks,

Hi,
Why 32-bit streams? What does the output from desktop simulation look like?
Stream width isn't an issue, the APU or PLB buses will transfer the correct amount of data. My previous post was about pointer alignment: Note that the use of 32-bit words does not guarantee 32-bit alignment in memory though your code may be showing everything 32-bit aligned just because that's how they stacked up.
Lastly, I'd double check the endian-ness of the data being packed into the 'left' and 'right' variables.

Ed

[Rock]

Hi,
Why 32-bit streams? What does the output from desktop simulation look like?
Stream width isn't an issue, the APU or PLB buses will transfer the correct amount of data. My previous post was about pointer alignment: Note that the use of 32-bit words does not guarantee 32-bit alignment in memory though your code may be showing everything 32-bit aligned just because that's how they stacked up.
Lastly, I'd double check the endian-ness of the data being packed into the 'left' and 'right' variables.

Ed

Hi Sir,
I assumed that both 32 bit varible alignment and 32 bit stream are needed for APU. I have gone through chapter regarding the program 3DES with microblaze processor in the text book "Practical FPGA Programming In C", there has given a 3DES code modification for a new communication scheme to improve the performance (with 32 bit streams). So i thought that modification is for APU.
Anyway i am still looking into the data alignment.

Thanks for the reply,

[Rock]

Hi Sir,

I have tried with the 32 bit variable alignments , though its not working. Getting same "D7 D7 D7..." from hardware.
As you said it is beacause of endianness, even i tried with sending the data in reverse order(MSB as LSB and LSB as MSB) but the same output.I have sent an email with the software code attached.
Please provide me any information..


Thanks

[Rock]

Hi all,


I have designed one Xilinx EDK(version 10.1) project which has UART16550, SYSACE with interrupts and added Tripple DES core(From Impulse Co-developer) with APU interface. This is working fine with the standalone environment. So i have generated BSP from this project and Configured the linux kernel. Linux is booting successfully with the combined bitstream.



I am trying to test the compiled (GCC PowerPC cross compiler) impulse C software executable in the linux environment.

When i try to run my software , Processor hanged after the 15th character in the first printf statement as shown below.



@#./3DES

@#

Impulse C 3DES D



all other programs working fine.


Please see the Software main() function below...



int main(int argc, char *argv[])

{

unsigned char * key = (unsigned char *) "Gflk jqo40978J0dmm$%@878"; /* 24 bytes */

co_architecture my_arch;

printf("Impulse C 3DES DEMO\n\r");

des3key(Ks, key, 0); /* Create a keyschedule for encryption */

printf("Running encryption test on FPGA ...\n\r");

my_arch = co_initialize((void *)Iterations);

co_execute(my_arch);

printf("Running encryption test on CPU ...\n\r");

des_c();

IF_SIM(printf("Press Enter key to continue...\n")

IF_SIM(c=getc(stdin)

return(0)

}



What could be the problem.



Any help would be appreciated





Thanks,



Reddy

[etrexel]

Hi all,


I have designed one Xilinx EDK(version 10.1) project which has UART16550, SYSACE with interrupts and added Tripple DES core(From Impulse Co-developer) with APU interface. This is working fine with the standalone environment. So i have generated BSP from this project and Configured the linux kernel. Linux is booting successfully with the combined bitstream.



I am trying to test the compiled (GCC PowerPC cross compiler) impulse C software executable in the linux environment.

When i try to run my software , Processor hanged after the 15th character in the first printf statement as shown below.

What could be the problem.

Any help would be appreciated

Thanks,
Reddy

Hi,
The timing of the printf() may just be a coincidence, using a debugger would be much more accurate. Also try running your exectuable in the background (using '&') and see if it or the CPU/OS is what is really hanging.
Now that you are running under a pre-emptive OS such as Linux, there is a good chance you will run into a known issue while accessing the APU interface, namely that the APU wrapper used does not handle instruction flushes correctly. To get around this you must ensure an instruction flush can not occur by disabling ALL interrupts. including the OS's tick counter used for task swapping. when the APU is being accessed. Personally, I do no tknow how to do this in Linux but do know it requires kernel level calls.

Ed