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[gc19861210]

the file Fir51_comp.vhd created by CoDeveloper automaticly is not complete,please see the file blow!!


-- ****************************************
-- DO NOT EDIT
-- This file was automatically generated by the Impulse C Compiler.
--
-- Impulse C is Copyright 2002-2005, Impulse Accelerated Technologies, Inc.
--
-- Stage Master is Copyright 2002-2005, Green Mountain Computing Systems, Inc.
--
-- All rights reserved.
--
-- ****************************************


-- TARGET: VHDL

library ieee;
use ieee.std_logic_1164.all;

package external_components is
end package;
library ieee;
use ieee.std_logic_1164.all;

library impulse;
use impulse.components.all;

entity fir is
port (signal reset : in std_ulogic;
signal sclk : in std_ulogic;
signal clk : in std_ulogic;
signal p_filter_in_rdy : in std_ulogic;
signal p_filter_in_en : inout std_ulogic;
signal p_filter_in_eos : in std_ulogic;
signal p_filter_in_data : in std_ulogic_vector (31 downto 0);
signal p_filter_out_rdy : in std_ulogic;
signal p_filter_out_en : inout std_ulogic;
signal p_filter_out_eos : out std_ulogic;
signal p_filter_out_data : out std_ulogic_vector (31 downto 0));
end fir;

use work.external_components.all;
architecture rtl of fir is
function mkvec(b : in std_ulogic) return std_ulogic_vector is
variable res : std_ulogic_vector(0 downto 0);
begin
res(0):=b;
return(res);
end;

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-- b1 stage 3
s_b1_vstall(3) <= '0';
ni3902_accum <= add(s_b1_2.f_accum, s_b1_2.f_r_e_g_3);
ni3904_accum <= add(ni3902_accum, s_b1_2.f_r_e_g_4);
ni3906_accum <= add(ni3904_accum, s_b1_2.f_r_e_g_5);
s_b1_vbreak(3) <= '0';
process (clk)
begin
if (clk'event and clk='1') then
if (s_b1_vwrite(3) = '1') then
s_b1_3.f_r_e_g_48 <= s_b1_2.f_r_e_g_48;
s_b1_3.f_r_e_g_47 <= s_b1_2.f_r_e_g_47;
s_b1_3.f_r_e_g_46 <= s_b1_2.f_r_e_g_46;
s_b1_3.f_r_e_g_45 <= s_b1_2.f_r_e_g_45;
s_b1_3.f_r_e_g_44 <= s_b1_2.f_r_e_g_44;
s_b1_3.f_r_e_g_43 <= s_b1_2.f_r_e_g_43;
s_b1_3.f_r_e_g_42 <= s_b1_2.f_r_e_g_42;
s_b1_3.f_r_e_g_41 <= s_b1_2.f_r_e_g_41;
s_b1_3.f_r_e_g_40 <= s_b1_2.f_r_e_g_40;
s_b1_3.f_r_e_g_39 <= s_b1_2.f_r_e_g_39;
s_b1_3.f_r_e_g_38 <= s_b1_2.f_r_e_g_38;
s_b1_3.f_r_e_g_37 <= s_b1_2.f_r_e_g_37;
s_b1_3.f_r_e_g_36 <= s_b1_2.f_r_e_g_36;
s_b1_3.f_r_e_g_35 <= s_b1_2.f_r_e_g_35;
s_b1_3.f_r_e_g_34 <= s_b1_2.f_r_e_g_34;
s_b1_3.f_r_e_g_33 <= s_b1_2.f_r_e_g_33;
s_b1_3.f_r_e_g_32 <= s_b1_2.f_r_e_g_32;
s_b1_3.f_r_e_g_31 <= s_b1_2.f_r_e_g_31;
s_b1_3.f_r_e_g_30 <= s_b1_2.f_r_e_g_30;
s_b1_3.f_r_e_g_29 <= s_b1_2.f_r_e_g_29;
s_b1_3.f_r_e_g_28 <= s_b1_2.f_r_e_g_28;
s_b1_3.f_r_e_g_27 <= s_b1_2.f_r_e_g_27;
s_b1_3.f_r_e_g_26 <= s_b1_2.f_r_e_g_26;
s_b1_3.f_r_e_g_25 <= s_b1_2.f_r_e_g_25;
s_b1_3.f_r_e_g_24 <= s_b1_2.f_r_e_g_24;
s_b1_3.f_r_e_g_23 <= s_b1_2.f_r_e_g_23;
s_b1_3.f_r_e_g_22 <= s_b1_2.f_r_e_g_22;
s_b1_3.f_r_e_g_21 <= s_b1_2.f_r_e_g_21;
s_b1_3.f_r_e_g_20 <= s_b1_2.f_r_e_g_20;
s_b1_3.f_r_e_g_19 <= s_b1_2.f_r_e_g_19;
s_b1_3.f_r_e_g_18 <= s_b1_2.f_r_e_g_18;
s_b1_3.f_r_e_g_17 <= s_b1_2.f_r_e_g_17;
s_b1_3.f_r_e_g_16 <= s_b1_2.f_r_e_g_16;
s_b1_3.f_r_e_g_15 <= s_b1_2.f_r_e_g_15;
s_b1_3.f_r_e_g_14 <= s_b1_2.f_r_e_g_14;
s_b1_3.f_r_e_g_13 <= s_b1_2.f_r_e_g_13;
s_b1_3.f_r_e_g_12 <= s_b1_2.f_r_e_g_12;
s_b1_3.f_r_e_g_11 <= s_b1_2.f_r_e_g_11;
s_b1_3.f_r_e_g_10 <= s_b1_2.f_r_e_g_10;
s_b1_3.f_r_e_g_9 <= s_b1_2.f_r_e_g_9;
s_b1_3.f_r_e_g_8 <= s_b1_2.f_r_e_g_8;
s_b1_3.f_r_e_g_7 <= s_b1_2.f_r_e_g_7;
s_b1_3.f_r_e_g_6 <= s_b1_2.f_r_e_g_6;
s_b1_3.f_r_e_g_5 <= s_b1_2.f_r_e_g_5;
s_b1_3.f_r_e_g_4 <= s_b1_2.f_r_e_g_4;
s_b1_3.f_r_e_g_3 <= s_b1_2.f_r_e_g_3;
s_b1_3.f_r_e_g_2 <= s_b1_2.f_r_e_g_2;
s_b1_3.f_r_e_g_1 <= s_b1_2.f_r_e_g_1;
s_b1_3.f_r_e_g_0 <= s_b1_2.f_r_e_g_0;
s_b1_3.f_accum <= ni3906_accum;
end if;
end if;
end process;

-- b1 stage 4
s_b1_vstall(4) <= '0';
ni3908_accum <= add(s_b1_3.f_accum, s_b1_3.f_r_e_g_6);
ni3910_accum <= add(ni3908_accum, s_b1_3.f_r_e_g_7);
ni3912_accum <= add(ni3910_accum, s_b1_3.f_r_e_g_8);
s_b1_vbreak(4) <= '0';
process (clk)
begin
if (clk'event and clk='1') then
if (s_b1_vwrite(4) = '1') then
s_b1_4.f_r_e_g_48 <= s_b1_3.f_r_e_g_48;
s_b1_4.f_r_e_g_47 <= s_b1_3.f_r_e_g_47;
s_b1_4.f_r_e_g_46 <= s_b1_3.f_r_e_g_46;
s_b1_4.f_r_e_g_45 <= s_b1_3.f_r_e_g_45;
s_b1_4.f_r_e_g_44 <= s_b1_3.f_r_e_g_44;
s_b1_4.f_r_e_g_43 <= s_b1_3.f_r_e_g_43;
s_b1_4.f_r_e_g_42 <= s_b1_3.f_r_e_g_42;
s_b1_4.f_r_e_g_41 <= s_b1_3.f_r_e_g_41;
s_b1_4.f_r_e_g_40 <= s_b1_3.f_r_e_g_40;
s_b1_4.f_r_e_g_39 <= s_b1_3.f_r_e_g_39;
s_b1_4.f_r_e_g_38 <= s_b1_3.f_r_e_g_38;
s_b1_4.f_r_e_g_37 <= s_b1_3.f_r_e_g_37;
s_b1_4.f_r_e_g_36 <= s_b1_3.f_r_e_g_36;
s_b1_4.f_r_e_g_35 <= s_b1_3.f_r_e_g_35;
s_b1_4.f_r_e_g_34 <= s_b1_3.f_r_e_g_34;
s_b1_4.f_r_e_g_33 <= s_b1_3.f_r_e_g_33;
s_b1_4.f_r_e_g_32 <= s_b1_3.f_r_e_g_32;
s_b1_4.f_r_e_g_31 <= s_b1_3.f_r_e_g_31;
s_b1_4.f_r_e_g_30 <= s_b1_3.f_r_e_g_30;
s_b1_4.f_r_e_g_29 <= s_b1_3.f_r_e_g_29;
s_b1_4.f_r_e_g_28 <= s_b1_3.f_r_e_g_28;
s_b1_4.f_r_e_g_27 <= s_b1_3.f_r_e_g_27;




it ends here.
I guess there are some problem here!
And there are other problem of the " Fir51"

[etrexel]

the file Fir51_comp.vhd created by CoDeveloper automaticly is not complete,please see the file blow!!

...
it ends here.
I guess there are some problem here!
And there are other problem of the " Fir51"

Hi,
What version are you using? And are you using the Examples\DSP\Fir51 excample unmodified? And what other problems are you encountering? An incomplete file would suggest a tool crash which will appear in the CoDeveloper.log file (and "Build" output window). I also just generated HDL for the Fir51 as-is under v3.20.a.5 with no errors.

Ed
Ed