1 reply to this topic

[romno]

I have successfully generated VHDL code from a reasonably-complex Impulse C file. I've successfully imported the VHDL into a Xilinx ISE project and am able to synthesize with no errors.

However, when I try to simulate using ModelSim, the simulation dies on an illegal address generation (address 20 is sent to a memory module with only 20 locations numbered 0 to 19). Has anyone else seen this issue? The memory module VHDL is shown below. I've done some digging, but haven't been able to track down the state machine that generates the illegal address on signal raddr2.

architecture dualsync of tsp20_main_current_RAM is
type memtype is array (0 to 19) of
std_ulogic_vector(31 downto 0);
signal mem : memtype := (
X"00000000",X"00000001",X"00000002",X"00000003",
X"00000004",X"00000005",X"00000006",X"00000007",
X"00000008",X"00000009",X"0000000a",X"0000000b",
X"0000000c",X"0000000d",X"0000000e",X"0000000f",
X"00000010",X"00000011",X"00000012",X"00000013");
signal raddr: unsigned(4 downto 0);
signal raddr2: unsigned(4 downto 0);
begin
writemem: process (clk)
begin
if (clk'event and clk='1') then
if (we = '1') then
mem(conv_integer(unsigned(addr))) <= din;
end if;
raddr <= unsigned(addr);
raddr2 <= unsigned(addr2);
end if;
end process;

dout <= mem(conv_integer(raddr));
dout2 <= mem(conv_integer(raddr2));
end dualsync;

[etrexel]

I have successfully generated VHDL code from a reasonably-complex Impulse C file. I've successfully imported the VHDL into a Xilinx ISE project and am able to synthesize with no errors.

However, when I try to simulate using ModelSim, the simulation dies on an illegal address generation (address 20 is sent to a memory module with only 20 locations numbered 0 to 19). Has anyone else seen this issue? The memory module VHDL is shown below. I've done some digging, but haven't been able to track down the state machine that generates the illegal address on signal raddr2.
...

Hi,
This is usually a side affect of using pipelines which can cause the index used on a memory array to be out of the defined range or using the same variable to access multiple different sized arrays. Because only the index is out of range and the memory is not actually being accessed, this is not a real error, but ModelSim doesn't see it that way. One workaround is to temporarily change the size of the array in your C code - making the size at least 2 times larger and then rounding up to a power of 2 will take care of all possibilities - when generating HDL for simulation. Please note that if the array has initialization values, there must be exactly the same number of constant values as there are locations in the array. #define's and #if-def's can also help with changing back and forth when targeting simulation or the target FPGA. Another workaround is to modify the HDL itself for more locations before simulation.

Ed