1 reply to this topic

[cls_egr]

Hi,

Where can I find general information about the number of multipliers that a multiplication requires, is there a one to one relation between the number of multipliers and the number of multiplications in a given application?

Thanks

cls

[etrexel]

Hi,

Where can I find general information about the number of multipliers that a multiplication requires, is there a one to one relation between the number of multipliers and the number of multiplications in a given application?

Thanks

cls

Hi,
As of v3.10.b.9 the summary outputted during HDL generation for Xilinx PSP's includes an estimate for DSP's which is essentially the number of multiplier units expected to be used. A sample of the output looks like:
|----------------------------------------
| Operators:
| 19 Adder(s)/Subtractor(s) (24 bit)
| 14 Adder(s)/Subtractor(s) (32 bit)
| 6 Multiplier(s) (16 bit)
| 1 Comparator(s) (2 bit)
|----------------------------------------
| Total Stages: 10
| Max. Unit Delay: 64
| Estimated DSPs: 6
|----------------------------------------

This is still of course an estimate and may change due to other factors such as synthesis optimizations and how mapping occurs - for instance due to the sharing of the "C" port of the DSP blocks within a Virtex-4 device it is possible for a design to effectively halve the number of DSP blocks available for a specific configuration.


Ed