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Apr 30 2008, 01:06 PM
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#1
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Advanced Member ![]() ![]() ![]() Group: Members Posts: 78 Joined: 11-July 06 Member No.: 694 |
Hi,
I am looking at Appendix B of the book, does the HDL transceiver is implemented in the Impulse C project as an external component using the CO_IMPLEMENTATION pragma? I was trying to find more information at website www.hylitech.com, but the site seems to be no longer available. I am trying to implement a different serial protocol between some boards. I have the HDL code for the communication, but I looking into way to integrate it within an Impulse C project. Thank you cls |
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Apr 30 2008, 02:12 PM
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#2
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Advanced Member ![]() ![]() ![]() Group: Impulse Staff Posts: 235 Joined: 20-April 06 Member No.: 594 |
Hi, I am looking at Appendix B of the book, does the HDL transceiver is implemented in the Impulse C project as an external component using the CO_IMPLEMENTATION pragma? I was trying to find more information at website www.hylitech.com, but the site seems to be no longer available. I am trying to implement a different serial protocol between some boards. I have the HDL code for the communication, but I looking into way to integrate it within an Impulse C project. Thank you cls Hi, #pragma CO IMPLEMENTATION cannot be used for conenctions to external HDL because it is used internally and does not have access to ports exposed in the generated top module in '_top.v/vhd. Connections to an Impulse C project must be made through the exposed interfaces for co_stream, co_signal, co_register, etc. which appear in the top module in '_top.v/vhd. Ed -------------------- Ed Trexel
Impulse Accelerated Technologies, Inc. |
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May 12 2008, 02:55 PM
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#3
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Advanced Member ![]() ![]() ![]() Group: Members Posts: 78 Joined: 11-July 06 Member No.: 694 |
Hi, #pragma CO IMPLEMENTATION cannot be used for conenctions to external HDL because it is used internally and does not have access to ports exposed in the generated top module in '_top.v/vhd. Connections to an Impulse C project must be made through the exposed interfaces for co_stream, co_signal, co_register, etc. which appear in the top module in '_top.v/vhd. Ed Hi, If the transceiver component in VHDL is not implemented as an external component using CO IMPLEMENTATION, is there any more detail information as to how the software program reaches to that transceiver component? Thank you cls |
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May 12 2008, 03:12 PM
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#4
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Advanced Member ![]() ![]() ![]() Group: Impulse Staff Posts: 235 Joined: 20-April 06 Member No.: 594 |
Hi, If the transceiver component in VHDL is not implemented as an external component using CO IMPLEMENTATION, is there any more detail information as to how the software program reaches to that transceiver component? Thank you cls Hi, Software<->hardware interaction is platform dependent and must be created by the user for platforms not already supportted by CoDeveloper. In my last post, the use of "internal" and "external" to describe HDL might have been a bit unclear, so just in case: There are essentially two user HDL interfaces to the HDL genereted by CoDeveloper: platform and user primitives. The platform interface is what appears either as the top module within the '_top.v/vhd or an automatically generated HDL wrapper for that same top module. This is what connects to the rest of the system within an FPGA, usually some sort of bus providing the hardware interface between the software application and hardware processes in the FPGA. User primitives are what allows a user to provide the HDL for a primitive function using the #pragma CO IMPLEMENTATION. A primitive function's HDL module is instantiated from within the generated '_comp.v/vhd file and is limited to only those connections appearing in that instantiation - this is why a primitive function cannot be used for I/O because it is not exposed through the top module to be connected to FPGA pins, buses, etc. Ed -------------------- Ed Trexel
Impulse Accelerated Technologies, Inc. |
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Jun 19 2008, 02:33 PM
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#5
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Advanced Member ![]() ![]() ![]() Group: Members Posts: 78 Joined: 11-July 06 Member No.: 694 |
Hi,
If I would like to use a different communication protocol like the one shown in the Practical FPGA Programming in C (or AP101). In order to use a VHDL code like the one for the transceiver there, in conjunction with the streams, how can I use the SW interface co_stream_read and write, but use a different hardware file? Thank you cls |
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Jun 19 2008, 07:50 PM
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#6
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Advanced Member ![]() ![]() ![]() Group: Impulse Staff Posts: 235 Joined: 20-April 06 Member No.: 594 |
Hi, If I would like to use a different communication protocol like the one shown in the Practical FPGA Programming in C (or AP101). In order to use a VHDL code like the one for the transceiver there, in conjunction with the streams, how can I use the SW interface co_stream_read and write, but use a different hardware file? Thank you cls Hi, You would need to create a new Platform Support Package (PSP) when defining custom hardware and/or software interfaces. For detailed documentation on creating a PSP, please see this thread: http://www.impulse-support.com/forums/inde...p?showtopic=342 Ed -------------------- Ed Trexel
Impulse Accelerated Technologies, Inc. |
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