Jump to content


HDL Simulation - FIR example


  • You cannot reply to this topic
4 replies to this topic

#1 cls_egr

    Advanced Member

  • Members
  • PipPipPip
  • 78 posts

Posted 24 January 2008 - 09:11 AM

Hi,

When I am trying to simulate the FIR example using a hardware simulation program I obtain errors in reading the data into and out of streams:

# ** Error: FIR.vhd(134): (vcom-1136) Unknown identifier "coef_table".
# ** Error: FIR.vhd(139): (vcom-1136) Unknown identifier "coef_count".

In addition, the command use work.config.all is not recognized.

Can someone give some guidance simulating this example in hardware?

Thanks

cls

#2 etrexel

    Advanced Member

  • Impulse Staff
  • PipPipPip
  • 260 posts

Posted 24 January 2008 - 06:44 PM

QUOTE (cls_egr @ Jan 24 2008, 10:11 AM) <{POST_SNAPBACK}>
Hi,

When I am trying to simulate the FIR example using a hardware simulation program I obtain errors in reading the data into and out of streams:

# ** Error: FIR.vhd(134): (vcom-1136) Unknown identifier "coef_table".
# ** Error: FIR.vhd(139): (vcom-1136) Unknown identifier "coef_count".

In addition, the command use work.config.all is not recognized.

Can someone give some guidance simulating this example in hardware?

Thanks

cls

Hi,
THe code in the book, specifically in regards to the HDL test bench, isn't terribly complete. The unknown identifiers are likely in an unpublished file that also defines the 'config' package. A similar and more up to date example would be from the CoDeveloper V2 installation at $IMPULSEC_HOME\Examples\Generic\Fir51 which contains a VHDL test bench in the included file 'test_fir.vhd'.

Ed
Ed Trexel
Impulse Accelerated Technologies, Inc.

#3 cls_egr

    Advanced Member

  • Members
  • PipPipPip
  • 78 posts

Posted 25 January 2008 - 08:29 AM

Thank you

cls

#4 cls_egr

    Advanced Member

  • Members
  • PipPipPip
  • 78 posts

Posted 25 January 2008 - 04:19 PM

Hi,

I was wondering, when does the rdy signal from the output stream is activated? Because throughout the HW simulation is 0, causing that data line from output stream be un-updated. Do you know where more information regarding stream interfaces protocol is available?

Thank you
cls

#5 etrexel

    Advanced Member

  • Impulse Staff
  • PipPipPip
  • 260 posts

Posted 25 January 2008 - 04:37 PM

QUOTE (cls_egr @ Jan 25 2008, 05:19 PM) <{POST_SNAPBACK}>
Hi,

I was wondering, when does the rdy signal from the output stream is activated? Because throughout the HW simulation is 0, causing that data line from output stream be un-updated. Do you know where more information regarding stream interfaces protocol is available?

Thank you
cls

Hi,
There is some documentation on the interfaces within the CoDeveloper user guide as well as APP108 available at: http://www.impulse-support.com/support_appnotes.htm

Generically: '_rdy is '1' when there is data available to be read from a stream or when data space is available to write to a stream. '_en indicates that the reader or writer is enabling a data transfer which each occurring during every clock cycle where both the '_rdy and '_en signals are both '1'.

Hope that helps,
Ed
Ed Trexel
Impulse Accelerated Technologies, Inc.





1 user(s) are reading this topic

0 members, 1 guests, 0 anonymous users