5 replies to this topic

[jungelism]

Hi,

I have 2 several CoDeveloper-projekts with HW-processes and want to conect them on an Xillinx XUP-Board with streams over the plb-bus.

I generated the Interfaces with the help of co_port_create. I instantiated the two Projekts in xps as slaves on the plb. While simulating the system in Modelsim the second process can't read the stream from the first one.

How can I manage it, that the two projekts communicate with each other?

Thanks

[etrexel]

How can I manage it, that the two projekts communicate with each other?

Thanks

Hi,
Is there a specific reason the projects are separated? If not, please note that an Impulse C project can contain many processes and many stream and other interfaces on the PLB bus.
If you still need to connect two projects, using the co_port_create() will expose the signals for a stream which then must be connected manually within XPS. One stream must be an co_port created as an "output" and the other must be created as an "input". To connect the two within XPS, create signal names for one of the streams and then assign them to the second criss-crossing the "*_en" and "*_rdy" signals like:
in_stream_data connects to out_stream_data
in_stream_eos connects to out_stream_eos
in_stream_rdy connects to out_stream_en
in_stream_en connects to out_stream_rdy

Hope that helps,
Ed

[RalphBodenner]

Looks like Ed beat me to an answer!

[jungelism]

hi,

what you've wrote sounds like a direkt connection bettween the two projekts.

But my problem is I have to use the plb-bus. Because in future there are more projekts and some with software parts which have to comunicate with one projekt written in VHDL, that have a managing function. And so I need the plb to comunicate and can't use direkt connections.

Is there a way to use the plb between the projekts when they are connected as slaves? I think the managerprojekt should be a master on the plb. But how can I manage it to make the Managerprojekt to become a master?

Thanks for your help.

[RalphBodenner]

Are you anticipating the use of an embedded PowerPC in future projects? It's easy to generate master-slave stream connections between PPC and FPGA using CoDeveloper, but using PLB to connect only hardware modules would involve some tweaking outside the compiler. PLB slaves can't communicate directly with each other.

For performance reasons, I would highly recommend using direct connections between hardware processes, and PLB to connect software processes with hardware. Impulse C streams can be used for both types of connections, and the compiler will generate the appropriate implementation.

[jungelism]

Thanks for your help,

I rethink my projekt and do it on an other way.