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[RalphBodenner]

Impulse Accelerated Technologies is pleased to make CoDeveloper Version 3.00.b.1 available to the public. This is a BETA release, meaning it has known bugs. However, this release offers numerous new features and bug fixes relative to the 2.20 release.

3.00.b.1:

• Updated documentation for Eclipse IDE
• New PSP: GiDEL PROCWizard
• New PSP: SGI RC100 (RASC)
• Replaced DRC RPU110-L200 PSP with updated VHDL version
• Updated Pico PSP for E-16; revised software driver for better performance, new bitfile build process
• Added ComplexFIR tutorial example for MicroBlaze and EDK 9.2i
• Bug fix: Error finding environment variable with recent Altera tools releases
• Bug fix: Error generating memory interfaces for Verilog platforms

3.00.a.22:

• Added DRC RPU110-L200 PSP v1.0
• Fix block RAM generation problem for Xilinx Verilog PSPs
• Completed Black-Scholes sample project
• Sync legacy IDE's Start Page sample projects with V3
• Fix titles of several Help windows
• Fix titles of many sample project Readmes
• Eclipse IDE
  • Fix bug where project templates were not shown when creating a new project
  • Clean up text of Sample Projects page, and other Welcome pages
• XtremeData XD1000 PSP
  • Fix typo in co_process.c
• Added licensing terms to Impulse IP libraries/cores

3.00.a.21:

• All PSP Help topics are now included in Eclipse
• Partially removed encryption example projects for export compliance
• XtremeData XD1000 PSP:
  • Allow up to 32 processes to be created in software
  • Update documentation for Quartus II 7.1
  • Fix error during synthesis where "mem_if_components" was not found

3.00.a.20:

• Eclipse IDE for managing Impulse C projects, including built-in C debugger
• Support for pipelining user-defined primitives
• Support for global array variables in co_memory_readblock and co_memory_writeblock
• Support for array offsets in co_memory block read/write operations
• Default locations for co_memory
• True dual-port memory for Altera FPGAs
• Xilinx PLB shared memory
• Shared memory I/O timing improvements
• Verilog floating-point support for Xilinx platforms, using XST
• Use divmod modules for modulus and division in Verilog
• Sample project: MicroBlaze MemoryIO example uses single-process producer/consumer
• Sample project: Fix 3DES example VHDL test bench stream timing errors
• Sample project: Fix compilation error in Mandelbrot sample for Virtex-4 APU under EDK 9.1i
• Bug fix: Close PLB hardware-to-software streams properly
• Bug fixes: FLATTEN pragma code generation
• Bug fix: Crash with pipelined primitive
• Bug fixes: Pipeline termination problems

Known issues include:

• Workspace directory path must not include a space, but this is not effectively enforced
• Building either Desktop Simulation configuration a second time causes an error ("multiple target patterns"); do Project > Clean between builds to work around this issue
• Project > Clean under Hardware configuration removes export directories
• Images not visible on the Eclipse Welcome page
• Opal Kelly Mandelbrot sample project missing
• Some PSPs are missing tutorials or documentation
• Nios II PSPs are not fully supported under Quartus II 7.2
• Issues reported in the Beta Release forum and not marked "FIXED"

Version 3 can be installed alongside Version 2. To switch between versions, change the IMPULSEC_HOME and IMPULSEC_GCC_HOME environment variables to point to the appropriate installation directories. Version 3 is installed in C:\Impulse\CoDeveloper3 by default.

The "legacy IDE" (from Version 2) is installed with this release, alongside the new Eclipse IDE. There is one major difference between the Version 2 IDE and the legacy IDE in Version 3: the legacy IDE uses the V3 compiler.

Download the release (Universal Edition only) here: http://impulsec.com/ReleaseFiles/Beta/CoDe...al_3.00.b.1.exe

As new Beta releases are made, this download link will go away and be superseded by the latest release.

If you are a Beta User, please post feedback on this release in the Beta Release forum.