Version 2.20.g.6 includes the following fixes and enhancements:
- Primitive functions can now be pipelined for higher performance
- Switch statements are now supported within if-statements
- A problem related to Xilinx APU co_stream_close has been fixed
- A probem related to Xilinx APU HW_STREAM_READ_NB macro return value has been fixed
- A problem with non-32-bit co_signals generated as co_ports has been fixed
- Various Verilog stream interface issues have been fixed
- A problem with global array synthesis has been fixed
- A problem with Xilinx floating-point division scheduling has been fixed












