6 replies to this topic

[Brett]

Is it possible to use both an OPB connection (co_memory) and an FSL connection (co_stream) within the same design?

If that's a problem, can I get around it by making two hardware modules and what restrictions would they have in communicating?

Brett

[RalphBodenner]

Yes, co_memory should fall back to using OPB in an otherwise FSL-based design.

[Brett]

Yes, co_memory should fall back to using OPB in an otherwise FSL-based design.

Ok, I took another swing at this and got a peripheral with both FSL & OPB connections but strangely, though I only created a single co_stream, I ended up with two FSL bus links. I'm attaching the modified memoryio files.

When implemented in EDK and downloaded, I get:

Memory read/write example for Xilinx external memory.

After tracing with gdb I find a stall in co_initialize in what I think is the first write to the fsl link. Apparently the producer/consumer never gets called.

Brett

Attached File(s)

•  MemoryIO_fsl_opb.zip (3.21K)
  Number of downloads: 12

[Brett]

Ok, I took another swing at this and got a peripheral with both FSL & OPB connections but strangely, though I only created a single co_stream, I ended up with two FSL bus links. I'm attaching the modified memoryio files.

When implemented in EDK and downloaded, I get:
After tracing with gdb I find a stall in co_initialize in what I think is the first write to the fsl link. Apparently the producer/consumer never gets called.

Brett

oops, I was mistaken, the jam actually happens inside the producer when it makes its first write to the FSL

CODE

put r19, rfsl0

Currently Ihave only one of the generated fsls connected, but it is connected to the ublaze fsl0 port.

Brett

[Brett]

oops, I was mistaken, the jam actually happens inside the producer when it makes its first write to the FSL

CODE

put r19, rfsl0

Currently Ihave only one of the generated fsls connected, but it is connected to the ublaze fsl0 port.

Brett

I still don't have this design working, but I may have a partial answer to one of my questions about why a single-stream design would have two fsl's. It would appear the second fsl is used to pass the memory-base address for the co_memory mechanism. I've attached the generated vhdl in a zip file. Why this method is used to pass the membase variable I don't know.

I'm still seeing the problem of the ublaze stalling at the first write to fsl0. An interesting note is that if I hook up the second fsl line it stalls inside co_initialize before it even gets to the producer. This time it stalls on the first write to fsl1 (the membase address). What would cause it to stall on my fsl links?

Brett

Attached File(s)

•  vhdl.zip (6.15K)
  Number of downloads: 2

[Brett]

I still don't have this design working, but I may have a partial answer to one of my questions about why a single-stream design would have two fsl's. It would appear the second fsl is used to pass the memory-base address for the co_memory mechanism. I've attached the generated vhdl in a zip file. Why this method is used to pass the membase variable I don't know.

I'm still seeing the problem of the ublaze stalling at the first write to fsl0. An interesting note is that if I hook up the second fsl line it stalls inside co_initialize before it even gets to the producer. This time it stalls on the first write to fsl1 (the membase address). What would cause it to stall on my fsl links?

Brett

arggg.... mea culpa.

No sooner had I written the last post that it occurred to me what was happening. The problem was that I hadn't connected my fsl_clk's correctly. Once that was fixed everything runs correctly. The modified example is attached for your convenience.

Attached File(s)

•  MemoryIO_fsl_mod.zip (101.59K)
  Number of downloads: 13

[micluha]

arggg.... mea culpa.

No sooner had I written the last post that it occurred to me what was happening. The problem was that I hadn't connected my fsl_clk's correctly. Once that was fixed everything runs correctly. The modified example is attached for your convenience.

I'm compiling the memoryIO_fsl project in EDK 9.1i and it fails when generating Virtual Platform - here is the log:
...
...

INFO:MDT -
Generating model for opb_mdm instance debug_module...

ERROR:MDT - ERROR while running cmodelgen
WARNING:MDT -
Generating dummy model for fsl_memoryio instance fsl_memoryio_0...
Done!!
ERROR:MDT - vpgen failed with errors!

This application has discovered an exceptional condition from which it cannot recover.
make: *** [virtualplatform/vpexec.exe] Error 2