2 replies to this topic

[Impulse Support]

A change was made in CoDeveloper version 1.22.d to the stream_dc.vhd and fifo_dc.vhd libraries. This change results in BRAM memories being generated by the XST synthesizer for stream buffers. In most cases this is the desired behavior and can dramatically reduce the amount of logic required to implemented a given process.

BRAM is a limited resource, however, and in some cases you may not wish to use BRAM for your stream buffers. If this is the case, you can suppress the generation of BRAM in the Xilinx XST synthesis tool by substituting the attached library files in your generated hardware (typically in the hw/vhdl/xilinx/lib directory within your project). These library files, which are taken from the version 1.22.c.6 release, generate logic rather than BRAM when synthesized in Xilinx XST.

Note that this is a tempory workaround: A future release of CoDeveloper will include more specific control over the type of memory generated for stream buffers.

Attached File(s)

•  xilinx_xst_bram_patch.zip (1.83K)
  Number of downloads: 46

[gchow]

Any update on this topic ? Seeing this was last discussed back in 2005, I am really hoping the feature has now been implemented. If so, a quick summary as to how to invoke it will be great. Thanks in advance.

[RalphBodenner]

Currently, the memory implementing stream buffers generally is inferred as distributed RAM by default in Xilinx platforms. Dual-clock streams (created when the "Generate dual clocks" compiler option is selected) will be inferred as block RAM.

To specify block RAM or single registers for implementing stream buffers, you can call the co_stream_config function:

CODE

co_error co_stream_config(co_stream stream, co_attribute attribute, const char *val);

You must call co_stream_config in the Impulse C configuration function, where streams and processes are created.

The 'attribute' parameter must take the value 'co_kind'.

The 'val' parameter's value selects the stream buffer implementation. Valid values for Xilinx platforms are:

• "reg": Single register buffer, one element deep
• "bram": Block RAM

By default, distributed RAM will be inferred for streams where co_stream_config is not use to specify a buffer implementation. This is not strictly true in all cases, however--the larger block RAMs may be inferred for large stream buffers. The final inference is left to the synthesis tool.