2 replies to this topic

[csullender]

The ZestSC1 board has a Spartan 3-1000 and 8MBytes ZBT SRAM. The board ships
with a memory interface in Verilog and VHDL.

I need to access the memory from 3 processes that read and one that writes.

I have seen the post "Rules for co_memory implementations in HDL?"
on two approaches:
1. connect an external memory to the Impulse C co_memory interface
like the Examples/Xilinx/SharedBRAM project "shared_mem.vhd" file.
2. modifying the Platform Support Package to create a wrapper for
the Impulse C shared memory interface that bridges between
Impulse C shared memory and the external memory controller

Do you have any other tips for the first approach? Do you have
an example like "shared_mem.vhd" in Verilog?

[csullender]

Also since I am processing pixels in pixel (x,y) order
the memory accesses are all in sequence from
address (start of image) to address (end of image).

So it shouldn't be too hard to interface to streams.

Stream creation such as
LS5r0 = co_stream_create("LS5r0", UINT_TYPE(16), BUFSIZE);
has a fifo buffer size at the end.

Where does this fifo live in hardware? In one of the processes
at one end of a stream? The process that writes to the stream?

[RalphBodenner]

I don't have any particular tips to offer regarding connecting a memory to the Impulse C shared memory interface. The shared_mem.vhd file is currently the best example of how to wire up the connection. You'll likely have to use some other synchronization mechanism (co_signals, for example) to ensure memory accesses among your processes don't conflict.

A stream's FIFO (see fifo.vhd) is instantiated in the 'stream' component (stream.vhd), which is instantiated in the top-level Impulse-generated file (*_top.vhd). You're free to replace stream.vhd and/or fifo.vhd with HDL of your own. The stream interface is documented in the CoDeveloper User's Guide (see CoDeveloper's Help menu). For each hardware stream connection (corresponding to a co_stream parameter in a hardware process), four ports appear on a hardware process module's port list. One 'stream' component is instantiated between the in and out ends of the stream. For a hardware-to-software (or hardware-to-co_port) stream, one end of that connection will be pulled up into the top-level's port list.