3 replies to this topic

[jacques]

Hallo

I have a problem with my design. One could say it ceased to function over the weekend. I have two PC's with Quartus, but one only has a web license (my laptop) that does not compile for my Stratix II DSP development board. It worked on Friday but didn't on Monday.

All new output pins that I add only gets X's (Forced unknown's) in the simulator. I thought a setting was wrong and couldn't find any problems. Eventually I took my old project from the unlicensed PC to the other machine. I then added an output just connected to the clock on both machines. On my laptop it was fine but not on the desktop PC. I further did a test by deleting a node wire and replacing it. After that, that output didn't work either. When deleting all signals in the .vwf file and re-adding them, nothing worked. If a new input is connected to a block, the compiler says that the input's are stuck at a value but doesn't on my laptop.

I uninstalled and reinstalled. Still the same. I also installed a second copy of Quartus and still the same thing happened. Does anyone know if it's a licensing issue or if a accidentally adjusted a setting that causes this?

Also, I am from South Africa and bandwidth is limited, so downloading service packs is considered a last resort.

Thank you
Jacques

[RalphBodenner]

Did you try re-creating the project from scratch, using the original source files?

[jacques]

Yes I did. Just connected a clock to an output pin and it does the same. A colleague of mine picked up the same problem. We both made new projects, tried old projects that used to work and tried to run the examples again with no luck. We also got hold of Quartus II 6.0 which does exactly the same. I'm really stumped on this one.

Thanks for your help.

[sdatta]

On the computer which is exhibiting these problems, bring up Quartus and do Tools->License Setup. If the license is expired you can get a new one from www.altera.com. Web Edition Licenses have hard expiry dates. If the license is not expired, remove the db directory, compile the design again, check the report file and check the logic equations for correctness. This looks like a fairly simple design so it can be verified without simulation. If the equations does not look right open a case at https://mysupport.altera.com/eservice/help/about_altera.asp


Hope this helps
Subroto Datta
Altera Corp.