Dual Ported RAM access from seperate hardware processes Options

[TonyP]

I am looking for an example of how to instantiate Xilinx dual-ported block RAM in the Impulse environment. I want to be able to write to one port with one hardware process and read the other port with another hardware process. Thanks.

[meix]

This question has been answered in support emails. Here is an excerpt from the email thread:

A global array may be created and accessed from two separate processes, each getting a separate port on the dual-port RAM created during synthesis. The multiple processes accessing a global array are then subject to the general rule that exists within all Xilinx PSP’s regarding dual-port RAM access in that one port may read and write while the other port may only read. A global array by default (co_array_config() does not currently affect global arrays) will be implemented as a dual-port synchronous RAM with the final decision on whether it is created in distributed or block RAM being made by XST.

Mei

I am looking for an example of how to instantiate Xilinx dual-ported block RAM in the Impulse environment. I want to be able to write to one port with one hardware process and read the other port with another hardware process. Thanks.