1 reply to this topic

[ureyhu]

Hello everybody.
In the first example "Hello FPGA" in the book <Practical FPGA Programming in C> , I meet some trouble.
When I simulate in the PC software , it 's quite normal. After the HDL files generated , I try to simulate them in Modelsim. However the result I got is weird. The input stream data is from 1 to 10. But only 2 4 6 8 ..10 appear in the output stream data . I don't know how to attach a file . I write the testbench key points below.
Thanks very much for your attention .


stimulus:process
variable k :integer := 0;
begin
p_producer_output_stream_en <= '0';
p_producer_output_stream_eos <='0';
p_producer_output_stream_data <= X"00";
wait for PERIOD;
while true loop
p_producer_output_stream_en <= '0';
if ( p_producer_output_stream_rdy = '1') then
p_producer_output_stream_data <= std_ulogic_vector(conv_std_logic_vector(k,8));
p_producer_output_stream_en <='1';
k:=k+1;
end if;
wait until rising_edge( clk);
if( k= 100) then
exit;
end if;
end loop;
wait;
end process stimulus;

result :process
begin
p_consumer_input_stream_en <= '1' ;
wait;
end process result;

Edited by ureyhu, 11 May 2010 - 06:10 PM.

[etrexel]

Hi,
It may be that the input data is being read every other cycle. To verify: look at the waveform, on the rising edge when p_producer_output_stream_rdy and p_producer_output_stream_en are both 1 is when the input data is sampled.

Best Regards,
Ed