3 replies to this topic

[ureyhu]

Happy New year , everybody.
I 'm trying to test the example "DCT" provided by ImpulseC . After I compile the project , I got two files DCT_comp.vhd and DCT_top.vhd and a directory called "lib" including a few files ,such as cregister.vhd,csignal.vhd,impack.vhd and so on. When I tried to compile the project in Quartus8.1, I encounted these errors :
Error (10324): VHDL Expression error at impack.vhd(271): expression ""000000"" has 6 elements ; expected 4 elements.
Error (10657): VHDL Subprogram error at DCT_comp.vhd(657): failed to elaborate call to subprogram "add"
Error: Can't elaborate user hierarchy "dct_run:dct"
It seems that error occurred form this sentence" ni729_r_e_g_0 <= add(shl(r_v, 3), "000000");" in the file DCT_comp.vhd
Thanks anyway

[etrexel]

Happy New year , everybody.
I 'm trying to test the example "DCT" provided by ImpulseC . After I compile the project , I got two files DCT_comp.vhd and DCT_top.vhd and a directory called "lib" including a few files ,such as cregister.vhd,csignal.vhd,impack.vhd and so on. When I tried to compile the project in Quartus8.1, I encounted these errors :
Error (10324): VHDL Expression error at impack.vhd(271): expression ""000000"" has 6 elements ; expected 4 elements.
Error (10657): VHDL Subprogram error at DCT_comp.vhd(657): failed to elaborate call to subprogram "add"
Error: Can't elaborate user hierarchy "dct_run:dct"
It seems that error occurred form this sentence" ni729_r_e_g_0 <= add(shl(r_v, 3), "000000");" in the file DCT_comp.vhd
Thanks anyway

Hi,
I am not able to reproduce the error and the line numbers above do not seem to match anything relevant. What version of CoDeveloper are you using? and what Platform Support Package (PSP) are you targeting?

Best Regards,
Ed

[ureyhu]

Hi,
I am not able to reproduce the error and the line numbers above do not seem to match anything relevant. What version of CoDeveloper are you using? and what Platform Support Package (PSP) are you targeting?

Best Regards,
Ed

That 's the point. I didn't select the fit PSP. In the "Project" - "Option" - "Generate" tab, I selected the "Generic VHDL" first , thus I encounter the error above in QuartusII 8.1 . If the "Alteral VHDL"tab is chosen , the compile process is quite normal without anything wrong. I'm using Quartus 8.1 and CoDeveloper 3.5.

BTW, I encounter another problem. In the same project , when I generated the ModelSim testbench , I found there files "compile.tcl " "setup.tcl" and "co_trace.vhd" . I 'm going to simulate the project in Modelsim 6.2 . what should I do ?
Is there any tutorial or suggestion about simulating in ModelSim ?

Thanks Ed .

[etrexel]

That 's the point. I didn't select the fit PSP. In the "Project" - "Option" - "Generate" tab, I selected the "Generic VHDL" first , thus I encounter the error above in QuartusII 8.1 . If the "Alteral VHDL"tab is chosen , the compile process is quite normal without anything wrong. I'm using Quartus 8.1 and CoDeveloper 3.5.

BTW, I encounter another problem. In the same project , when I generated the ModelSim testbench , I found there files "compile.tcl " "setup.tcl" and "co_trace.vhd" . I 'm going to simulate the project in Modelsim 6.2 . what should I do ?
Is there any tutorial or suggestion about simulating in ModelSim ?

Thanks Ed .

Hi,
I'll make a note of the error when selecting the "Generic(VHDL)" PSP to be fixed. In general, the vendor specific PSP (Altera, Xilinx, etc.) should always be chosen for best results. I would also recommend using the latest version of CoDeveloper currently 3.60.b.7.
Regarding the ModelSim testbench (works with ANY version 6.x ModelSim): Please see the section "CoValidator Testbench Generator" in the Impulse C User Guide for details on using CoValidator - please note that it does assume the user is familiar with using ModelSim for the actual HDL simulation.

Best Regards,
Ed