The software simulation works fine. But when I try to generate hdl or launch hardware simulation, it tries to generate, take its time, log all stage information, but at the end impulse_genvhdl.exe fails to generate design_name_comp.vhdl.
It works fine for other smaller designs, but gets stuck here.
What is the reason for this failure? Is there a way to overcome this error?
Is there a way to make output more verbose OR debug enable for impulse_genvhdl.exe ?
The last part of log generated is as under:
CODE
|----------------------------------------
| Operators:
| 2 Adder(s)/Subtractor(s) (8 bit)
| 2145 Adder(s)/Subtractor(s) (9 bit)
| 82 Adder(s)/Subtractor(s) (11 bit)
| 7 Adder(s)/Subtractor(s) (13 bit)
| 2653 Adder(s)/Subtractor(s) (32 bit)
| 1 Comparator(s) (2 bit)
| 4615 Comparator(s) (32 bit)
|----------------------------------------
| Total Stages: 16459
| Max. Unit Delay: 64
| Estimated DSPs: 0
|----------------------------------------
Writing output ... done
"C:/Impulse/CoDeveloper3/bin/impulse_arch" "-aC:/Impulse/CoDeveloper3/Architectures/altera_nios2.xml" -swdirsw -files "hmmer_partitioned_comp.vhd hmmer_partitioned_top.vhd " hmmer_partitioned.xic hw/hmmer_partitioned_top.vhd
Impulse C HDL Design Generator
Copyright 2002-2009, Impulse Accelerated Technologies, Inc.
All rights reserved.
Loading C:/Impulse/CoDeveloper3/Architectures/altera_nios2.xml ...
Loading C:/Impulse/CoDeveloper3/Architectures/VHDL/Altera/Avalon/bus.xml ...
Loading C:/Impulse/CoDeveloper3/Architectures/VHDL/target.xml ...
Loading C:/Impulse/CoDeveloper3/Architectures/VHDL/Altera/technology.xml ...
Loading C:/Impulse/CoDeveloper3/Architectures/VHDL/Generic/Generic/system.xml ...
Loading hmmer_partitioned.xic ...
"C:/Impulse/CoDeveloper3/bin/impulse_genvhdl.exe" hmmer_partitioned.xhw hw/hmmer_partitioned_comp.vhd
make: *** [hw/hmmer_partitioned_comp.vhd] Error 1
======== Build of target 'build' complete ========
| Operators:
| 2 Adder(s)/Subtractor(s) (8 bit)
| 2145 Adder(s)/Subtractor(s) (9 bit)
| 82 Adder(s)/Subtractor(s) (11 bit)
| 7 Adder(s)/Subtractor(s) (13 bit)
| 2653 Adder(s)/Subtractor(s) (32 bit)
| 1 Comparator(s) (2 bit)
| 4615 Comparator(s) (32 bit)
|----------------------------------------
| Total Stages: 16459
| Max. Unit Delay: 64
| Estimated DSPs: 0
|----------------------------------------
Writing output ... done
"C:/Impulse/CoDeveloper3/bin/impulse_arch" "-aC:/Impulse/CoDeveloper3/Architectures/altera_nios2.xml" -swdirsw -files "hmmer_partitioned_comp.vhd hmmer_partitioned_top.vhd " hmmer_partitioned.xic hw/hmmer_partitioned_top.vhd
Impulse C HDL Design Generator
Copyright 2002-2009, Impulse Accelerated Technologies, Inc.
All rights reserved.
Loading C:/Impulse/CoDeveloper3/Architectures/altera_nios2.xml ...
Loading C:/Impulse/CoDeveloper3/Architectures/VHDL/Altera/Avalon/bus.xml ...
Loading C:/Impulse/CoDeveloper3/Architectures/VHDL/target.xml ...
Loading C:/Impulse/CoDeveloper3/Architectures/VHDL/Altera/technology.xml ...
Loading C:/Impulse/CoDeveloper3/Architectures/VHDL/Generic/Generic/system.xml ...
Loading hmmer_partitioned.xic ...
"C:/Impulse/CoDeveloper3/bin/impulse_genvhdl.exe" hmmer_partitioned.xhw hw/hmmer_partitioned_comp.vhd
make: *** [hw/hmmer_partitioned_comp.vhd] Error 1
======== Build of target 'build' complete ========











