2 replies to this topic

[Laviewwx]

Hi all,

I met a problem about USER_LOGIC_MD_MODULE_0_CONFIG_BASE in compiling the makefile, the original error message is
/*******************************************/
gcc -I inc -I linux_driver -c -o co_init.o -O2 -Wall co_init.c
co_init.c: In function âco_initializeâ:
co_init.c:68: error: âUSER_LOGIC_MD_MODULE_0_CONFIG_BASEâ undeclared (first use in this function)
co_init.c:68: error: (Each undeclared identifier is reported only once
co_init.c:68: error: for each function it appears in.)
make: *** [co_init.o] Error 1
/*******************************************/

the problematic code in the co_init.c are

co_memory_attach(Input_memory, xd_fpga_handle, ZBT_SRAM_AVALON_0_BASE, USER_LOGIC_MD_MODULE_0_CONFIG_BASE);
co_memory_attach(Output_memory, xd_fpga_handle, ZBT_SRAM_AVALON_0_BASE, USER_LOGIC_MD_MODULE_0_CONFIG_BASE);

I have a reference design which works perfect, it also have the same declaration of SDRAM, so I am confused and may anyone give me some hint about the error code?

I assume the USER_LOGIC_MD_MODULE_0_CONFIG_BASE specifies the memory bank that FPGA uses, is it problematic that I target all my three HW processes to the same "PE0"? The place and route is done w/o error.

Sorry to post it twice in the general discussion section.

Thank you
Weixin

[etrexel]

Hi all,

I met a problem about USER_LOGIC_MD_MODULE_0_CONFIG_BASE in compiling the makefile, the original error message is
/*******************************************/
gcc -I inc -I linux_driver -c -o co_init.o -O2 -Wall co_init.c
co_init.c: In function âco_initializeâ:
co_init.c:68: error: âUSER_LOGIC_MD_MODULE_0_CONFIG_BASEâ undeclared (first use in this function)
co_init.c:68: error: (Each undeclared identifier is reported only once
co_init.c:68: error: for each function it appears in.)
make: *** [co_init.o] Error 1
/*******************************************/

the problematic code in the co_init.c are

co_memory_attach(Input_memory, xd_fpga_handle, ZBT_SRAM_AVALON_0_BASE, USER_LOGIC_MD_MODULE_0_CONFIG_BASE);
co_memory_attach(Output_memory, xd_fpga_handle, ZBT_SRAM_AVALON_0_BASE, USER_LOGIC_MD_MODULE_0_CONFIG_BASE);

I have a reference design which works perfect, it also have the same declaration of SDRAM, so I am confused and may anyone give me some hint about the error code?

I assume the USER_LOGIC_MD_MODULE_0_CONFIG_BASE specifies the memory bank that FPGA uses, is it problematic that I target all my three HW processes to the same "PE0"? The place and route is done w/o error.

Sorry to post it twice in the general discussion section.

Thank you
Weixin

Hi,
The error appears to be just that the compiler cannot find USER_LOGIC_MD_MODULE_0_CONFIG_BASE defined, look in the co_init.c file itself and the files included. It may have to do with the names for the module and/or memory used and comparing names used against the reference design may help find where it is.

Best Regards,
Ed

[Laviewwx]

Hi,
The error appears to be just that the compiler cannot find USER_LOGIC_MD_MODULE_0_CONFIG_BASE defined, look in the co_init.c file itself and the files included. It may have to do with the names for the module and/or memory used and comparing names used against the reference design may help find where it is.

Best Regards,
Ed

Ed,

Thank you for the reply, problem solved after i rebuild a new project elsewhere, though i did not really figure out exactly where the problem is...

Weixin