1 reply to this topic

[bizertino]

Hi,

i m still trying to control hardware generation. This time i m trying to make sequential multiplication not parallel one. here an example :

res1 = a*b ;
res2 = d*c ;
var1 = e*f ;

normally if i generate this in hardware it results on 3 parallel multipliers (depends on targeted FPGA) but we admit that hardware resources are available,
but if i want to do this 3 multiplications with only 1 multiplier with sequential manner (like in a normal processor), of course it will be much time consuming but in my case the purpose it is to control hardware utilization.

Is there any solution to do this type of generation?

thanks

[etrexel]

Hi,

i m still trying to control hardware generation. This time i m trying to make sequential multiplication not parallel one. here an example :

res1 = a*b ;
res2 = d*c ;
var1 = e*f ;

normally if i generate this in hardware it results on 3 parallel multipliers (depends on targeted FPGA) but we admit that hardware resources are available,
but if i want to do this 3 multiplications with only 1 multiplier with sequential manner (like in a normal processor), of course it will be much time consuming but in my case the purpose it is to control hardware utilization.

Is there any solution to do this type of generation?

thanks

Hi,
The translation from C to HDL is largely literal in that for every operator that appears in the C code (in this case each '*'), equivalent hardware resources for each operator is instantiated. So basically to reduce the resources the operator's appearance must be reduced which may be done using a loop and then multiplexing the multiplicands and result like:

CODE

      for(i=0;i<3;i++) {
         if(i=0) {m1=a; m2=b;}
         else if(i=1) {m1=d;m2=c;}
         ...
         result = m1 * m2;
         if(i=0) res1=result;
       else if(i=1) res2=result;
         ...
      }

or using an index into arrays:

CODE

        for(i=0;i<3;i++) {
         result[i] = m1[i] * m2[i];
        }

Best Regards,
Ed