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How to control hardware generation ?


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#1 bizertino

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Posted 14 September 2009 - 02:00 AM

Hi,

my application includes many multiplications and divisions (in float). It induces a considerable use of hardware multipliers. I want to maintain this format but to control generated hardware area eg. to limit multiplier number usage. Actually i m studying the CO PRIMITIVE initiative to generate a hardware module to handle some of those multiplications and division hoping that can reduce multiplier usage unsure.gif . I m asking if there is any alternative solution ?

thx for help


#2 Impulse Support

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Posted 21 September 2009 - 07:10 AM

Floating point applications can certainly use large amounts of FPGA resources. We can only make general suggestions regarding limiting the required resources, for example:
  • Use a hardware primitive to create specialized functions, for example shift operations or exponentiations, to reduce the need for multipliers and dividers. The "CordicMath" example shows the basic method, as does the financial example "EuropeanOptions".
  • Precompute values when possible.
  • Reduce the use of double types.
  • Use fixed point if practical, using the macros we provide.
  • Use reduced-width integers (such as co_uint13) to match required numeric ranges, for example when maintaining a counter.
  • Avoid loop unrolling or manually unroll to control the size of generated logic.
  • Be careful with calling hardware primitive functions, as each call generates a new instance of the function in hardware.

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#3 bizertino

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Posted 23 September 2009 - 03:00 AM

thanks, will try and let users informed.





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