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[schmidtmeier]

We have slightly modified one of the image processing examples and encountered problems during the simulation with Modelsim. The simulator stops with a fatal error because of a wrong memory access. We examined the problem and found interesting effects. The sw simulation is running properly. But an error during hw simulation occurred if we generate the code as 'Xilinx Generic (VHDL)'. If we use 'Generic (VHDL)' the hw simulation is running properly. Here is the simplified piece of code:

CODE

        
         for ( kidx = 0; kidx < MEMSIZE; kidx++ ){
         co_stream_read(input_stream, &MEM[kidx], sizeof(STREAMTYPE));
         }
         //oldpix = MEM[0];
         for (nidx = 0; nidx < MEMSIZE; nidx++ ) {
         oldpix = MEM[nidx];
         co_stream_read(input_stream, &newpix, sizeof(STREAMTYPE));
         co_stream_write(output_stream, &oldpix, sizeof(STREAMTYPE));
         MEM[nidx] = newpix;
         }

By the way if we uncomment the line with the oldpix variable the code is also running properly in hw simulation. In VHDL there is an additional state if the line is uncommented.

We are using Version 3.10.